sep

Integrate the SEP security processor CPU, crypto, IO, SMN, and lifecycle boundaries.

Exposes JTAG, DMI, memory-macro, SMN AXI, crypto SRAM, eFuse, SPI, lifecycle, mailbox, and Key Manager error interfaces to the integrator. sep_global_base_addr_o and sep_region_size_o publish the SEP aperture from sep_cpu_ctrl CSRs for the SMU AXI crossbar SEP-target rule. External-aperture requests inside the eFuse shim CSR window are diverted to the eFuse wrapper; the rest leave on sep_external_axi_req_o through an axi_cut. PIC source i+1 is internal interrupt i for the NUM_INTERNAL_IRQS internal sources (mailbox, DMA, WDT, SPI, crypto, eFuse and bridge faults), followed by extintsrc_req_i. The WDT bark drives the CPU NMI, which jumps to SEP_NMI_VEC. When unused, tie test_en_i to 1'b0 and scan_rst_ni to 1'b1.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`KM_LATCHED_MEM_RDATA`	`bit`	`1'b1`	1 if Key Manager ROM/SRAM latch read data for look-ahead.
`ABR_MASKING_EN`	`bit`	`1'b1`	Enable Adams Bridge 2-share DOM masking.
`ABR_SRAM_LATENCY`	`int unsigned`	`1`	Adams Bridge SRAM read latency in cycles.
`EXT_TRNG_NUM_AXIS`	`int unsigned`	`3`	Number of external TRNG AXI-Stream ports; must be 3, one per entropy mux leg.
`EFUSE_SHIM_SIZE`	`int unsigned`	`'h4`	Size in bytes of the eFuse shim CSR window diverted from the external aperture to the eFuse wrapper.
`SEP_SEC_DISABLE_TOKEN`	`bit [255:0]`	`256'b0`	Netlist-embedded secure-disable token digest; replace at synthesis.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`clk_ref_i`	input	`logic`	Free-running reference clock for REFERENCE_COUNTER.
`clk_wdt_i`	input	`logic`	200 kHz watchdog counter clock, asynchronous to clk_i.
`rst_ni`	input	`logic`	Active-low reset. Unless the JTAG override forces it, the SEP reset derived from it is released only after fuse sensing and ext_boot_seq_done_i.
`dbg_rstb_i`	input	`logic`	EL2 debug-module reset, active-low.
`wdt_rst_ni`	input	`logic`	Aggregated WDT resets from SMC and SEP, active-low; resets only the CPU.
`wdt_timer_rst_req_o`	output	`logic`	SEP WDT bite reset request, active-high, to the SMC reset unit.
`jtag_tck_i`	input	`logic`	JTAG clock.
`jtag_tms_i`	input	`logic`	JTAG test mode select, sampled on jtag_tck_i.
`jtag_tdi_i`	input	`logic`	JTAG test data input, sampled on jtag_tck_i.
`jtag_trst_ni`	input	`logic`	JTAG reset, active-low.
`jtag_tdo_o`	output	`logic`	JTAG test data output; valid while jtag_tdoEn_o is high.
`jtag_tdoEn_o`	output	`logic`	JTAG TDO output enable.
`jtag_sep_reset_ctrl_i`	input	`sep_pkg::jtag_sep_reset_ctrl_t`	JTAG IC_RESET override and value bits for the SEP reset and the per-engine crypto resets, in the TCK domain.
`axil_sep_otp_jtag_req_i`	input	`sep_efuse_pkg::efuse_axil_req_t`	OTP debug AXI-Lite manager request to the eFuse wrapper; answered with DECERR in restricted lifecycle states.
`axil_sep_otp_jtag_resp_o`	output	`sep_efuse_pkg::efuse_axil_resp_t`	OTP debug AXI-Lite manager response.
`mpc_debug_halt_req_i`	input	`logic`	Async MPC debug halt request.
`mpc_debug_run_req_i`	input	`logic`	Async MPC debug run request.
`mpc_reset_run_req_i`	input	`logic`	1 to run and 0 to halt in debug mode after reset.
`cpu_halt_req_i`	input	`logic`	Async halt request to the CPU.
`cpu_run_req_i`	input	`logic`	Async restart request to the CPU.
`test_en_i`	input	`logic`	DFT test-enable / scan-enable; tie 1'b0 when unused.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low, for reset synchronizer bypass; tie 1'b1 when unused.
`ext_boot_seq_done_i`	input	`logic`	Integration boot-sequence completion (memory repair and SMC straps); gates release of the SEP reset.
`dmi_core_enable_i`	input	`logic`	Enables DMI accesses to the core debug module registers.
`dmi_uncore_enable_i`	input	`logic`	Enables DMI accesses to the uncore aperture of the DMI address space.
`dmi_uncore_en_o`	output	`logic`	DMI access strobe to the uncore aperture, gated by dmi_uncore_enable_i.
`dmi_uncore_wr_en_o`	output	`logic`	Write qualifier for the uncore DMI access; low for reads.
`dmi_uncore_addr_o`	output	`logic [6:0]`	DMI register address of the uncore access.
`dmi_uncore_wdata_o`	output	`logic [31:0]`	Write data of the uncore DMI access.
`dmi_uncore_rdata_i`	input	`logic [31:0]`	Read data returned by the uncore for the addressed DMI register.
`dmi_active_o`	output	`logic`	High while the debug transport drives a DMI access to the core or uncore.
`sep_cpu_trace_o`	output	`sep_pkg::sep_cpu_trace_t`	Core instruction trace: retired instruction, address, valid, exception, cause, interrupt, and tval.
`lockstep_ctrl_i`	input	`sep_pkg::sep_lockstep_ctrl_t`	CPU lockstep control; inert unless built with RV_LOCKSTEP_ENABLE.
`lockstep_status_o`	output	`sep_pkg::sep_lockstep_status_t`	CPU lockstep status; inert unless built with RV_LOCKSTEP_ENABLE.
`jtag_id_i`	input	`logic [31:1]`	JTAG IDCODE bits [31:1] reported by the core debug TAP; bit 0 is fixed at 1.
`timer_int_i`	input	`logic`	Machine timer interrupt to the core.
`soft_int_i`	input	`logic`	Machine software interrupt to the core.
`extintsrc_req_i`	input	`logic [sep_pkg::NUM_EXTERNAL_IRQS-1:0]`	External interrupt requests; bit i is PIC source NUM_INTERNAL_IRQS + i + 1.
`sep_cpu_tcm_req_o`	output	`sep_pkg::sep_cpu_tcm_req_t`	Per-bank ICCM and DCCM macro requests, with the macro clock, to sep_tcm_wrapper.
`sep_cpu_tcm_rsp_i`	input	`sep_pkg::sep_cpu_tcm_rsp_t`	Per-bank ICCM and DCCM read data and ECC from sep_tcm_wrapper.
`sep_sram_req_o`	output	`sep_pkg::sep_sram_req_t`	Request from the SEP SRAM memory interface to the SRAM macro.
`sep_sram_rsp_i`	input	`sep_pkg::sep_sram_rsp_t`	Read data from the SEP SRAM macro.
`sep_boot_rom_req_o`	output	`sep_pkg::sep_sram_req_t`	Request from the boot ROM memory interface to the ROM macro.
`sep_boot_rom_rsp_i`	input	`sep_pkg::sep_sram_rsp_t`	Read data from the boot ROM macro.
`smn_outbound_axi_req_o`	output	`sep_pkg::sep_system_peripherals_outbound_axi_req_t`	Outbound request to the SMN after the outbound filter.
`smn_outbound_axi_resp_i`	input	`sep_pkg::sep_system_peripherals_outbound_axi_resp_t`	Outbound response from the SMN.
`smn_inbound_axi_req_i`	input	`sep_pkg::sep_system_peripherals_internal_axi_req_t`	SMN inbound request with a 56-bit global address, before the inbound filter.
`smn_inbound_axi_resp_o`	output	`sep_pkg::sep_system_peripherals_internal_axi_resp_t`	SMN inbound response.
`sep_ext_to_smc_axi_req_o`	output	`sep_pkg::sep_system_peripherals_internal_axi_req_t`	SEP request in the SMC aperture, after the alias remap; not filtered.
`sep_ext_to_smc_axi_resp_i`	input	`sep_pkg::sep_system_peripherals_internal_axi_resp_t`	Response from the SMC to sep_ext_to_smc_axi_req_o.
`entropy_rosc_sample_clk_i`	input	`logic`	Ring-oscillator sample clock for entropy_source; async vs clk_i, ~100-400 MHz typical.
`sep_crypto_pka_imem_sram_req_o`	output	`sep_crypto_pkg::sep_crypto_pka_imem_sram_req_t`	OTBN IMEM SRAM request from prim_ram_1p_scr_ext.
`sep_crypto_pka_imem_sram_rsp_i`	input	`sep_crypto_pkg::sep_crypto_pka_imem_sram_rsp_t`	OTBN IMEM SRAM response.
`sep_crypto_pka_dmem_sram_req_o`	output	`sep_crypto_pkg::sep_crypto_pka_dmem_sram_req_t`	OTBN DMEM SRAM request from prim_ram_1p_scr_ext.
`sep_crypto_pka_dmem_sram_rsp_i`	input	`sep_crypto_pkg::sep_crypto_pka_dmem_sram_rsp_t`	OTBN DMEM SRAM response.
`abr_mem_req_o`	output	`sep_crypto_pkg::abr_mem_req_t`	Adams Bridge external SRAM request; tech macros in sep_ip_integration.
`abr_mem_rsp_i`	input	`sep_crypto_pkg::abr_mem_rsp_t`	Adams Bridge external SRAM response.
`ext_trng_axil_req_o`	output	`sep_pkg::sep_32_32_axil_req_t`	External TRNG register request for 0x1091_7000-0x1091_7FFF, passed through to sep_ip_integration.
`ext_trng_axil_resp_i`	input	`sep_pkg::sep_32_32_axil_resp_t`	External TRNG AXI-Lite passthrough response.
`ext_trng_axis_req_i`	input	`sep_crypto_pkg::ext_trng_axis_req_t`	External TRNG streams from sep_ip_integration; stream i feeds entropy mux leg i (0 Key Manager, 1 AES/KMAC/OTBN, 2 entropy pool).
`ext_trng_axis_rsp_o`	output	`sep_crypto_pkg::ext_trng_axis_rsp_t`	tready to each external TRNG stream: the consumer's tready when selected, held high to drain the stream when not.
`ext_trng_irq_i`	input	`logic`	External TRNG interrupt; PIC source 17.
`km_rom_mem_req_o`	output	`km_intf_pkg::km_rom_mem_req_t`	Key Manager request to its 16 KiB ROM hard macro.
`km_rom_mem_rsp_i`	input	`km_intf_pkg::km_rom_mem_rsp_t`	Read data from the Key Manager ROM hard macro.
`km_sram_mem_req_o`	output	`km_intf_pkg::km_sram_mem_req_t`	Key Manager request to its 32 KiB SRAM hard macro.
`km_sram_mem_rsp_i`	input	`km_intf_pkg::km_sram_mem_rsp_t`	Read data from the Key Manager SRAM hard macro.
`efuse_bank_ctrl_req_o`	output	`sep_efuse_pkg::efuse_axil_req_t`	eFuse bank control AXI-Lite request to the shim CSR.
`efuse_bank_ctrl_resp_i`	input	`sep_efuse_pkg::efuse_axil_resp_t`	eFuse bank control AXI-Lite response.
`efuse_shim_command_req_o`	output	`sep_efuse_pkg::fuse_command_req_t`	eFuse read and program commands on the custom shim command interface.
`efuse_shim_command_resp_i`	input	`sep_efuse_pkg::fuse_command_resp_t`	Shim response to the eFuse commands.
`lcc_demote_state_1_o`	output	`logic [1:0]`	Differentially encoded DEMOTE_1.demote bit, which re-opens debug feature bits [23:0] in TEST_DEV and PROD; to the SMC.
`lcc_demote_state_2_o`	output	`logic [1:0]`	Differentially encoded DEMOTE_2.demote bit, which re-opens debug feature bits [47:24] in TEST_DEV and PROD; to the SMC.
`sep_io_spi_req_o`	output	`sep_io_pkg::sep_io_spi_req_t`	SPI pad outputs (clock, chip select, 4 data lanes and their output enables), plus the SPI interrupt and DMA trigger.
`sep_io_spi_rsp_i`	input	`sep_io_pkg::sep_io_spi_rsp_t`	SPI data-lane inputs from the pads.
`lc_state_o`	output	`logic [2*sep_pkg::LcStateBitWidth-1:0]`	Differentially encoded lifecycle state from the eFuse shadow registers.
`dbg_disable_o`	output	`sep_lifecycle_ctrl_pkg::dbg_disable_t`	Per-interface debug disables for the DTP, active-high (1 = disabled).
`sep_fuse_dft_disable_o`	output	`logic`	Disables the SEP fuse DFT access path, active-high; no functional consumer, provided for DFT insertion.
`smc_fuse_dft_disable_o`	output	`logic`	Disables the SMC fuse DFT access path, active-high; no functional consumer, provided for DFT insertion.
`lc_sigint_err_o`	output	`logic`	Integrity error on the differentially encoded LC state; forces every feature enable off unless security is disabled.
`security_disable_o`	output	`logic`	Security-disable status from eFuse token processing, active-high.
`secure_tm_o`	output	`logic`	Latched secure test mode, active-high; captured on the second clock edge after rst_ni release when security is disabled, otherwise when fuse sensing finishes.
`smc_mailbox_interrupt_o`	output	`logic [sep_pkg::NumMailboxes-1:0]`	Per-mailbox outbound-data interrupts to the SMC.
`smc_fuse_sense_done_i`	input	`logic`	SMC fuse sense completion, reflected in SMC_FUSE_SENSE_STATUS; requests to the SMC hang while it is low.
`sep_fuse_sense_done_o`	output	`logic`	High once the SEP eFuse shadow registers have been loaded from the fuses.
`secure_tm_req_i`	input	`logic`	Secure test mode request strap, latched into secure_tm_o.
`sep_external_axi_req_o`	output	`sep_pkg::sep_32_64_6_12_axi_req_t`	Request for the external aperture 0x2000_0000-0x3FFF_FFFF outside the eFuse shim window.
`sep_external_axi_resp_i`	input	`sep_pkg::sep_32_64_6_12_axi_resp_t`	Response to sep_external_axi_req_o.
`smc_global_base_addr_i`	input	`logic [sep_pkg::SEP_SYSTEM_PERIPHERALS_56_ADDR_WIDTH-1:0]`	Base of the SMC aperture in the global address map; SEP requests inside it leave on sep_ext_to_smc_axi_req_o.
`smc_region_size_i`	input	`logic [sep_pkg::SEP_SYSTEM_PERIPHERALS_56_ADDR_WIDTH-1:0]`	Size in bytes of the SMC aperture at smc_global_base_addr_i.
`sep_global_base_addr_o`	output	`logic [sep_pkg::SEP_SYSTEM_PERIPHERALS_56_ADDR_WIDTH-1:0]`	SEP global base address from sep_cpu_ctrl; SMU crossbar SEP-target rule.
`sep_region_size_o`	output	`logic [sep_pkg::SEP_SYSTEM_PERIPHERALS_56_ADDR_WIDTH-1:0]`	SEP region size from sep_cpu_ctrl; SMU crossbar SEP-target rule.
`km_unrecoverable_err_o`	output	`logic`	Key Manager unrecoverable fault, active-high: its CPU is in the trap state and no longer executing; also PIC source 31.
`km_recoverable_err_o`	output	`logic`	Key Manager recoverable-fault indication; also PIC source 32.
`ext_debug_bus_o`	output	`logic [383:0]`	24 lanes of 16 bits: CPU trace and control status, interrupts, reset and security status, eFuse, remap and filter debug; bits [159:0] are 0.