sep_cpu

Wrap the VeeR EL2 core complex behind a mostly core-agnostic SEP CPU boundary.

Contains the RV32 core, PIC, and debug module with the ICCM and DCCM controllers; the TCM RAM macros sit outside, in sep_tcm_wrapper. The core boots from the boot ROM base and core_id is 0. The external interface is mostly not EL2-specific so another core can replace EL2 with limited churn above.

VeeR reset bypass (scan_rst_n) is not exposed on the el2_veer_wrapper boundary. Lockstep ctrl/status ports stay present even when RV_LOCKSTEP_ENABLE is off so the hierarchy above keeps one footprint.

The LSU, IFU and debug masters first pass through a window remap that rewrites addresses in [sep_local_base_addr_i, sep_local_base_addr_i + 0x3000_0000) to 0x1000_0000 plus the offset. An IFU demux then sends boot ROM addresses to the ROM port, SEP SRAM addresses to the SRAM port, and everything else to a DECERR slave; an LSU demux sends boot ROM addresses to the ROM port and everything else to the xbar port. Master AxUSER carries SepSourceId and AtoP is 0. The TCM structs connect to sep_tcm_wrapper, instantiated in sep_ip_integration.

nmi_vec_i and jtag_id_i should be tied to constants or sourced from a CSR.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset.
`dbg_rstb_i`	input	`logic`	EL2 debug-module reset, active-low; also resets the mpc_reset_run_req_i synchronizer.
`jtag_tck_i`	input	`logic`	JTAG test clock of the core debug TAP.
`jtag_tms_i`	input	`logic`	JTAG test mode select, sampled on jtag_tck_i.
`jtag_tdi_i`	input	`logic`	JTAG test data input, sampled on jtag_tck_i.
`jtag_trst_ni`	input	`logic`	JTAG TAP reset, active-low.
`jtag_tdo_o`	output	`logic`	JTAG test data output; valid while jtag_tdoEn_o is high.
`jtag_tdoEn_o`	output	`logic`	JTAG Test Data Output enable.
`mpc_debug_halt_req_i`	input	`logic`	Asynchronous multi-processor-controller debug halt request.
`mpc_debug_run_req_i`	input	`logic`	Asynchronous multi-processor-controller debug run request.
`mpc_reset_run_req_i`	input	`logic`	1 to run and 0 to halt in debug mode after reset; synchronized to clk_i here.
`mpc_debug_halt_ack_o`	output	`logic`	Acknowledge of mpc_debug_halt_req_i.
`mpc_debug_run_ack_o`	output	`logic`	Acknowledge of mpc_debug_run_req_i.
`debug_brkpt_status_o`	output	`logic`	Debug breakpoint status from the core.
`cpu_halt_req_i`	input	`logic`	Async halt req to CPU.
`cpu_halt_ack_o`	output	`logic`	Core acknowledge of cpu_halt_req_i.
`cpu_halt_status_o`	output	`logic`	High while the core is halted.
`debug_mode_status_o`	output	`logic`	High while the core is in debug mode; the power manager must not send a halt or run request then.
`cpu_run_req_i`	input	`logic`	Async restart req to CPU.
`cpu_run_ack_o`	output	`logic`	Core response to run req.
`test_en_i`	input	`logic`	DFT test-enable (scan-enable) to the core scan_mode and the demux test inputs.
`dmi_core_enable_i`	input	`logic`	Enables DMI accesses to the core debug module registers.
`dmi_uncore_enable_i`	input	`logic`	Enables DMI accesses to the uncore aperture of the DMI address space.
`dmi_uncore_en_o`	output	`logic`	DMI access strobe to the uncore aperture, gated by dmi_uncore_enable_i.
`dmi_uncore_wr_en_o`	output	`logic`	Write qualifier for the uncore DMI access; low for reads.
`dmi_uncore_addr_o`	output	`logic [6:0]`	DMI register address of the uncore access.
`dmi_uncore_wdata_o`	output	`logic [31:0]`	Write data of the uncore DMI access.
`dmi_uncore_rdata_i`	input	`logic [31:0]`	Read data returned by the uncore for the addressed DMI register.
`dmi_active_o`	output	`logic`	High while the debug transport drives a DMI access to the core or uncore.
`nmi_vec_i`	input	`logic [31:1]`	PC bits [31:1] the core jumps to on an NMI.
`jtag_id_i`	input	`logic [31:1]`	JTAG IDCODE bits [31:1] reported by the core debug TAP; bit 0 is fixed at 1.
`nmi_int_i`	input	`logic`	Non-maskable interrupt to the core; hold for at least two clk_i cycles.
`timer_int_i`	input	`logic`	Machine timer interrupt to the core.
`soft_int_i`	input	`logic`	Machine software interrupt to the core.
`extintsrc_req_i`	input	`logic [sep_pkg::SEP_CPU_IRQ_WIDTH-1:0]`	External interrupt requests to the core PIC; bit i is PIC source i+1.
`sep_cpu_trace_o`	output	`sep_pkg::sep_cpu_trace_t`	Core instruction trace: retired instruction, address, valid, exception, cause, interrupt, and tval.
`iccm_ecc_single_error_o`	output	`logic`	ICCM single-bit (corrected) ECC error indication from the core.
`iccm_ecc_double_error_o`	output	`logic`	ICCM double-bit (uncorrectable) ECC error indication from the core.
`dccm_ecc_single_error_o`	output	`logic`	DCCM single-bit (corrected) ECC error indication from the core.
`dccm_ecc_double_error_o`	output	`logic`	DCCM double-bit (uncorrectable) ECC error indication from the core.
`dec_tlu_perfcnt0_o`	output	`logic`	Toggles when slot0 perf counter 0 has an event increment.
`dec_tlu_perfcnt1_o`	output	`logic`	Toggles when slot0 perf counter 1 has an event increment.
`dec_tlu_perfcnt2_o`	output	`logic`	Toggles when slot0 perf counter 2 has an event increment.
`dec_tlu_perfcnt3_o`	output	`logic`	Toggles when slot0 perf counter 3 has an event increment.
`lockstep_ctrl_i`	input	`sep_pkg::sep_lockstep_ctrl_t`	Lockstep corruption-detection disable and error-injection enable; ignored unless built with RV_LOCKSTEP_ENABLE.
`lockstep_status_o`	output	`sep_pkg::sep_lockstep_status_t`	Lockstep corruption-detected status; held at zero unless built with RV_LOCKSTEP_ENABLE.
`sep_cpu_tcm_req_o`	output	`sep_pkg::sep_cpu_tcm_req_t`	Per-bank ICCM and DCCM macro requests, with the macro clock, to sep_tcm_wrapper.
`sep_cpu_tcm_rsp_i`	input	`sep_pkg::sep_cpu_tcm_rsp_t`	Per-bank ICCM and DCCM read data and ECC from sep_tcm_wrapper.
`ifu_rom_axi_req_o`	output	`sep_pkg::sep_32_64_3_12_axi_req_t`	IFU fetch request for boot ROM addresses.
`ifu_rom_axi_resp_i`	input	`sep_pkg::sep_32_64_3_12_axi_resp_t`	IFU fetch response from the boot ROM.
`ifu_sram_axi_req_o`	output	`sep_pkg::sep_32_64_3_12_axi_req_t`	IFU fetch request for SEP SRAM addresses.
`ifu_sram_axi_resp_i`	input	`sep_pkg::sep_32_64_3_12_axi_resp_t`	IFU fetch response from the SEP SRAM.
`lsu_rom_axi_req_o`	output	`sep_pkg::sep_32_64_3_12_axi_req_t`	LSU request for boot ROM addresses.
`lsu_rom_axi_resp_i`	input	`sep_pkg::sep_32_64_3_12_axi_resp_t`	LSU response from the boot ROM.
`lsu_xbar_axi_req_o`	output	`sep_pkg::sep_32_64_3_12_axi_req_t`	LSU request for every address outside the boot ROM, to the SEP local xbar.
`lsu_xbar_axi_resp_i`	input	`sep_pkg::sep_32_64_3_12_axi_resp_t`	LSU response from the SEP local xbar.
`dbg_axi_req_o`	output	`sep_pkg::sep_32_64_3_12_axi_req_t`	Debug-module system-bus request, after the local alias remap.
`dbg_axi_resp_i`	input	`sep_pkg::sep_32_64_3_12_axi_resp_t`	Debug-module system-bus response.
`cpu_tcm_axi_req_i`	input	`sep_pkg::sep_32_64_6_12_axi_req_t`	Request into the core DMA slave port for ICCM and DCCM access.
`cpu_tcm_axi_resp_o`	output	`sep_pkg::sep_32_64_6_12_axi_resp_t`	Response from the core DMA slave port; B and R USER carry SepSourceId.
`sep_local_base_addr_i`	input	`logic [31:0]`	Base of the SEP local alias window; LSU, IFU, and debug addresses inside it are remapped to 0x1000_0000 plus the offset.