sep_crypto_abr_wrapper

Integrate Caliptra Adams Bridge into the SEP crypto subsystem as the PQC engine.

Convert host AXI (64-bit) to 32-bit AXI to AXI4-Lite to axi_lite_to_ahb for abr_top AHB (64-bit data / 32-bit addr), one transfer on the AHB at a time. The AXCACHE modifiable bit is forced so 64-bit beats can be split; only full-word writes reach abr_top, and writes with all byte strobes low complete with OKAY without an AHB transfer. abr_top has no entropy port and its scan-mode zeroize input is tied low.

Terminate the Key Manager private 32-bit AXI4-Lite key bus on abr_wrapper_key_reg here; sep_abr_kv_shim turns that hwif into Caliptra KV ports. The shim serves:

ML-DSA seed on kv_read[0].
ML-KEM seed D||Z on kv_read[1].
ML-KEM msg on kv_read[2].

The shim also implements ML-KEM kv_write into MLKEM_SHARED_KEY with key_valid / IRQ_STATUS hwset. mlkem_sharedkey_irq_o exposes the gated interrupt. ML-KEM has no engine driver yet, so its lanes are DV-stimulus-only.

Technology SRAM macros are not instantiated here. abr_mem_req_t / abr_mem_rsp_t thread to sep_ip_integration. Word-write channels are we/re/addr/data; sig_z and pk also carry one-bit-per-byte wstrobe.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MASKING_EN`	`bit`	`1`	Enables 2-share DOM masking in abr_top.
`SRAM_LATENCY`	`int unsigned`	`1`	Read latency of the external Adams Bridge SRAMs in cycles, passed to abr_top.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock; also forwarded to the SRAM macros in abr_mem_req_o.
`rst_ni`	input	`logic`	Active-low reset.
`abr_axi_req_i`	input	`sep_pkg::sep_32_64_6_12_axi_req_t`	Host 64-bit AXI4 control/status request, bridged to the abr_top AHB slave; in sep_crypto the demux rejects bursts before this port.
`abr_axi_resp_o`	output	`sep_pkg::sep_32_64_6_12_axi_resp_t`	Response on the host control/status port.
`abr_key_axil_req_i`	input	`km_intf_pkg::km_axil_req_t`	Key Manager private 32-bit AXI4-Lite key bus; terminates on the internal abr_wrapper_key_reg CSR block (u_abr_key_csr).
`abr_key_axil_resp_o`	output	`km_intf_pkg::km_axil_resp_t`	Response from the Adams Bridge key CSR block to the Key Manager.
`abr_mem_req_o`	output	`abr_mem_req_t`	abr_top requests to its external SRAM macros, which live in sep_ip_integration, packed into one struct together with the macro clock.
`abr_mem_rsp_i`	input	`abr_mem_rsp_t`	Read data from the external Adams Bridge SRAM macros.
`scan_mode_i`	input	`logic`	DFT scan mode; drives only the test input of the AXI-to-AXI-Lite converter.
`mlkem_sharedkey_irq_o`	output	`logic`	Level ML-KEM shared-key-ready interrupt: IRQ_STATUS.key_valid gated by IRQ_ENABLE.key_valid_en.
`error_intr_o`	output	`logic`	Adams Bridge global error interrupt, from the abr_top interrupt block.
`notif_intr_o`	output	`logic`	Adams Bridge global notification interrupt; set on command completion.
`busy_o`	output	`logic`	High while the Adams Bridge engine is not idle.