sep_dma_wrap

Bridge AXI register and host ports onto the secure_dma TileLink UL core.

Register path: 64-bit AXI is downsized to 32 bits, rebased by subtracting SEP_TOP_SECURE_DMA_BASE_ADDR, converted to AXI-Lite and then to TL-UL. Master path: TL-UL is converted to AXI-Lite, then to AXI with AxCACHE 0 and AxPROT 3'b001 (privileged, secure, data), upsized to 64 bits, and passed through a window remap that rewrites addresses in [sep_local_base_addr_i, sep_local_base_addr_i + 0x3000_0000) to 0x1000_0000 plus the offset. The CTN and system interfaces and the RACL policies are tied off.

dma_alert_o aggregates the fatal alert pulse with integ_fail of all channels.

dma_reg_bus_err_o and dma_host_intg_err_o stick until dma_err_clr_i; a fault arriving in the same cycle as the clear still latches. They are not cleared by a CPU-only reset (sep_cpu_reset_n is a subset of this block's rst_ni), so firmware must treat an assertion at boot as possibly stale.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`REG_ADDR_WIDTH`	`int unsigned`	`32`	Width of SECURE_DMA_REG_MAP_BASE_ADDR only; unused otherwise.
`SECURE_DMA_REG_MAP_BASE_ADDR`	`bit [REG_ADDR_WIDTH-1:0]`	`32'h20000000`	Unused; the register path rebases with SEP_TOP_SECURE_DMA_BASE_ADDR instead.
`ALERT_ASYNC_ON`	`logic [secure_dma_reg_pkg::NumAlerts-1:0]`	`{secure_dma_reg_pkg::NumAlerts{1'b1}}`	Per-alert async-on configuration of the secure_dma senders; the local receivers are synchronous.
`ALERT_SKEW_CYCLES`	`int unsigned`	`1`	Alert skew cycle count.
`ENABLE_DATA_INTG_GEN`	`bit`	`1'b1`	Generate TL-UL integrity in secure_dma, command and data integrity on the register bridge, and response and data integrity on the host bridge.
`ENABLE_RSP_DATA_INTG_CHECK`	`bit`	`1'b1`	Check response data integrity in secure_dma and command integrity of its host requests in the host bridge.
`TL_USER_RSVD`	`logic [tlul_pkg::RSVD_WIDTH-1:0]`	`'0`	Reserved TL user bits.
`SYS_RACL_ROLE`	`top_racl_pkg::racl_role_t`	`'0`	System RACL role.
`OT_AGENT_ID`	`int unsigned`	`0`	OpenTitan agent ID.
`ENABLE_RACL`	`bit`	`1'b0`	Enable RACL checks.
`RACL_ERROR_RSP`	`bit`	`ENABLE_RACL`	Return error responses on RACL fail.
`RACL_POLICY_SEL_VEC`	`top_racl_pkg::racl_policy_sel_t`	`'{secure_dma_reg_pkg::NumRegs{0}}`	Per-register RACL policy select.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset.
`test_en_i`	input	`logic`	DFT test-enable (scan-enable).
`lsio_trigger_i`	input	`secure_dma_pkg::lsio_trigger_t`	Peripheral handshake signalling that data is ready for the DMA to transfer.
`intr_dma_done_o`	output	`logic`	Secure DMA transfer-done interrupt.
`intr_dma_chunk_done_o`	output	`logic`	Secure DMA chunk-done interrupt.
`intr_dma_error_o`	output	`logic`	Secure DMA error interrupt.
`dma_alert_o`	output	`logic`	OR of the alert pulses and integrity failures of the local receivers for every secure_dma alert.
`dma_reg_bus_err_o`	output	`logic`	Register-path fault, set when the register bridge receives a TL-UL error response. Held until dma_err_clr_i, and firmware must treat an assertion at boot as possibly stale rather than a fresh fault.
`dma_host_intg_err_o`	output	`logic`	DMA-master-path fault from the TL-UL to AXI-Lite bridge: a non-OKAY AXI response or a failed TL-UL command-integrity check.
`dma_err_clr_i`	input	`logic`	Single-cycle clear for dma_reg_bus_err_o and dma_host_intg_err_o, pulsed by DMA_BUS_ERR_CLEAR in sep.
`reg_req_i`	input	`sep_pkg::sep_32_64_6_12_axi_req_t`	64-bit AXI register request to the secure_dma CSRs, with absolute addresses.
`reg_resp_o`	output	`sep_pkg::sep_32_64_6_12_axi_resp_t`	64-bit AXI register response from the secure_dma CSRs.
`dma_req_o`	output	`sep_pkg::sep_32_64_3_12_axi_req_t`	64-bit AXI DMA master request, after the local alias remap.
`dma_resp_i`	input	`sep_pkg::sep_32_64_3_12_axi_resp_t`	64-bit AXI DMA master response.
`sep_local_base_addr_i`	input	`logic [31:0]`	Base of the SEP local alias window; DMA master addresses within 0x3000_0000 above it are remapped to 0x1000_0000 plus the offset.