sep_entropy_fifo

Pack native EDN entropy into a fabric FIFO drained by a read-only AXI aperture.

Pull conditioned, FIPS-marked 32-bit words from a native OpenTitan EDN endpoint routed out of sep_crypto, pack 32 to 64, and buffer them in a synchronous FIFO. Software (EL2 host, debug, or an external agent) drains the pool through a 64-bit read-only AXI-Lite aperture on sep_local_axi_xbar. Datapath: EDN handshake adapter (req_pending_q) into prim_packer_fifo (InW=32, OutW=64, ClearOnRead=0), then prim_fifo_sync (Width=64, Depth=FIFO_DEPTH). AXI-Lite decode of the 16-bit offset is 0x00 status, 0x08 irq-cause, 0x10 data pop; a pop of an empty pool and any other offset return SLVERR with zero data. One read is outstanding at a time. The pool FIFO has no hardened pointers, so pool_err_o is always 0. The AXI connectivity matrix grants a (master, slave) pair as a single bit and cannot mask direction, so AW/W/B arrive whenever any master has read access. Every write terminates in place with BRESP=SLVERR and no state change; that SLVERR is the read-only enforcement because entropy enters only via the native EDN bus. FIFO_DEPTH defaults to 32 packed 64-bit entries. LOW_WATERMARK defaults to 8. STALL_THRESH defaults to 4096 cycles (~20 us at 200 MHz) with a request outstanding and no EDN acknowledge, and clears on the next ack; the stall detector arms on the first acknowledge after reset or entropy_clear_i.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`FIFO_DEPTH`	`int unsigned`	`32`	Pool depth in packed 64-bit entries (default 32); at most 63 to fit the status occupancy field.
`LOW_WATERMARK`	`int unsigned`	`8`	Occupancy below which pool_low_o asserts (default 8).
`STALL_THRESH`	`int unsigned`	`4096`	Outstanding EDN cycles before fill_stall_o (default 4096, ~20 us at 200 MHz); clears on next ack.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset.
`entropy_clear_i`	input	`logic`	Synchronous clear, active-high, while the internal TRNG is in reset. Scrubs only entropy-path state; the AXI responder stays alive and reports empty.
`test_en_i`	input	`logic`	Test-mode enable for the internal AXI to AXI-Lite converter.
`edn_req_o`	output	`edn_req_t`	Native EDN fill request, raised only while both the pool and the packer have room; a hardware pull, not an AXI bus.
`edn_rsp_i`	input	`edn_rsp_t`	Native EDN fill response; each acknowledge delivers one 32-bit word.
`entropy_fifo_axi_req_i`	input	`axi_req_t`	Full AXI4 drain request from sep_local_axi_xbar; every write completes with SLVERR and no state change.
`entropy_fifo_axi_resp_o`	output	`axi_resp_t`	Full AXI4 drain response to sep_local_axi_xbar.
`pool_low_o`	output	`logic`	Occupancy below LOW_WATERMARK, and high during entropy_clear_i; routed to the SEP PIC.
`fill_stall_o`	output	`logic`	EDN not acknowledging for more than STALL_THRESH cycles; fault to the SEP PIC.
`pool_err_o`	output	`logic`	Pool pointer-integrity fault; always 0 because the pool FIFO has no hardened pointers.
`fifo_level_o`	output	`logic [$clog2(FIFO_DEPTH+1)-1:0]`	Current occupancy in packed 64-bit entries; 0 during entropy_clear_i.