sep_ot_spi_wrap

Bridge AXI4-Lite onto the OpenTitan spi_host TL-UL register interface.

Follows the crypto-accelerator pattern: unmodified spi_host on native TL-UL, with axi_lite_to_tlul presenting the 32-bit AXI4-Lite bus from sep_io. Addresses are rebased by the SPI controller base and masked to the 6-bit spi_host window. Writes with all byte strobes low complete locally with OKAY and never reach the core. The bridge's sticky fault output is left unconnected.

The upstream REGGEN block is authoritative for the register map:

INTR_STATE is RW1C.
INTR_ENABLE gates only the interrupt output.
INTR_TEST is a write pulse.

irq_o is the OR of the core's error and spi_event lines. lsio_trigger_o is passed through. There is no busy output; activity is STATUS.ACTIVE over the register interface.

RACL is compiled out (EnableRacl = 0) with inactive policies. The spi_device passthrough is held inactive. The single fatal alert (bus integrity) is terminated here because sep_io has no alert path.

Supports:

A configurable number of chip selects (default 1).
Up to Quad SPI.
Single transfer rate only (no DTR/DDR).
Software-driven command sequences without memory-mapped XIP flash access.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_CS`	`int unsigned`	`1`	Number of SPI chip selects.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset.
`test_en_i`	input	`logic`	DFT test-enable (scan-enable).
`axil_req_i`	input	`sep_io_pkg::axil_req_t`	spi_host register request; 0x10B0_0000 - 0x10B0_0037 (56 bytes) in the SEP address map.
`axil_resp_o`	output	`sep_io_pkg::axil_resp_t`	spi_host register response from the TL-UL bridge.
`spi_sck_o`	output	`logic`	SPI serial clock to the pad.
`spi_sck_oe_o`	output	`logic`	Output enable for the SPI serial clock pad, active-high.
`spi_cs_no`	output	`logic [NUM_CS-1:0]`	Active-low chip selects to the pads.
`spi_cs_oe_o`	output	`logic [NUM_CS-1:0]`	Output enables for the chip-select pads, active-high.
`spi_sd_o`	output	`logic [3:0]`	Output data on the four SPI data lanes.
`spi_sd_oe_o`	output	`logic [3:0]`	Per-lane output enables for the SPI data pads, active-high.
`spi_sd_i`	input	`logic [3:0]`	Input data from the four SPI data lanes.
`irq_o`	output	`logic`	SPI interrupt: OR of the spi_host error and spi_event interrupts.
`lsio_trigger_o`	output	`logic`	spi_host DMA trigger, passed through.