sep_reset_ctrl

Sequence software resets for Key Manager and crypto accelerators through isolation.

Each bit in the SW_RESET_N register drives a sep_isolate_rst_seq FSM that requests isolation of that domain's AXI paths, waits for them to drain, and then asserts the domain's sequenced reset. An engine domain isolates its host path and its KM path; the KM domain isolates the KM paths to every engine and to eFuse; the TRNG domain isolates the entropy-source, CSRNG and EDN paths. Each sequenced reset is ANDed with the SEP reset, then the synchronized JTAG IC_RESET override for KM, OTBN, AES, HMAC, KMAC, ABR, or the internal TRNG complex selects its value, and in test mode scan_rst_ni replaces the result. SW_RESET_N bits: 0 km_sw_rst_n, 1 otbn_sw_rst_n, 2 aes_sw_rst_n, 3 hmac_sw_rst_n, 4 kmac_sw_rst_n, 5 trng_sw_rst_n, 6 abr_sw_rst_n; write 1 to release from reset, 0 to hold. KM resets to 0 (held in reset) and the others to 1. The register block and the AXI converter are reset by the SEP reset; the FSMs and synchronizers by rst_ni. Register map: hw/sys/sep/regs/blocks/sep_reset_ctrl/sep_reset_ctrl.rdl.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`rst_ni`	input	`logic`	Active-low reset of the isolation FSMs and the JTAG override synchronizers.
`wdt_rst_ni`	input	`logic`	Aggregated WDT resets from SMC and SEP, active-low; resets only the CPU.
`jtag_sep_reset_ctrl_i`	input	`sep_pkg::jtag_sep_reset_ctrl_t`	JTAG IC_RESET override and value bits in the TCK domain. The per-IP bits pass through 2-flop synchronizers into clk_i; the SEP reset override acts asynchronously ahead of the SEP reset synchronizer.
`sep_intermediate_reset_ni`	input	`logic`	Active-low SEP reset before the JTAG override, released by sep_efuse_wrapper once fuse sensing is done.
`sep_reset_no`	output	`logic`	Active-low SEP reset after the JTAG override, asserted asynchronously and released synchronously to clk_i through a 2-flop synchronizer; scan_rst_ni in test mode.
`sep_reset_ctrl_axi_req_i`	input	`sep_pkg::sep_32_64_6_12_axi_req_t`	AXI4 slave (full AXI from top-level SEP local xbar). An internal axi_to_axi_lite converter feeds the AXI-Lite reg block.
`sep_reset_ctrl_axi_resp_o`	output	`sep_pkg::sep_32_64_6_12_axi_resp_t`	Full AXI response to the SEP local xbar.
`test_en_i`	input	`logic`	DFT test-enable (scan-enable).
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low; replaces the SEP reset synchronizer output and every reset output while test_en_i is high.
`sep_cpu_reset_no`	output	`logic`	Active-low CPU reset: the SEP reset ANDed with wdt_rst_ni, or scan_rst_ni in test mode.
`sep_crypto_isolate_req_o`	output	`sep_pkg::sep_crypto_isolate_t`	Per-path isolation request to sep_crypto's AXI interconnect, active-high. A KM path is requested when either its engine or the KM domain is being reset.
`sep_crypto_isolated_i`	input	`sep_pkg::sep_crypto_isolate_t`	Per-path isolation acknowledge from sep_crypto's AXI interconnect, same layout as sep_crypto_isolate_req_o.
`sep_crypto_gated_rst_no`	output	`sep_pkg::sep_sw_rst_t`	Isolation-sequenced resets to sep_crypto, active-low, one per SW_RESET_N domain; also asserted by the SEP reset and forced by the JTAG overrides.