sep_sram

Declare the port list of a SEP SRAM controller front-end for an external technology SRAM macro.

The module body is empty: no output is driven and no input is used. The port clauses describe the intended interface: macro pins synchronous to sram_ck_o, an active-low chip enable and write enable, a clock stall, and a wipe command for the data memory.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`DWIDTH`	`int unsigned`	`32`	Intended SRAM data width in bits; sizes the macro ports only.
`PWIDTH`	`int unsigned`	`5`	Intended SRAM parity width in bits; sizes the macro data ports only.
`AWIDTH`	`int unsigned`	`14`	Intended SRAM address width in bits; sizes sram_a_o only.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock; unused.
`rst_ni`	input	`logic`	Active-low reset; unused.
`stall_i`	input	`logic`	Intended macro clock stall; unused.
`wipe_i`	input	`logic`	Intended command to clear the data memory; unused.
`irq_o`	output	`logic`	Intended interrupt request; undriven.
`error_o`	output	`logic [7:0]`	Intended error status with no defined encoding; undriven.
`sram_ck_o`	output	`logic`	Intended macro clock to which all macro operations are synchronous; undriven.
`sram_cs_no`	output	`logic`	Intended macro chip enable, active-low; undriven.
`sram_wen_o`	output	`logic`	Intended macro write enable, active-low; undriven.
`sram_bwen_o`	output	`logic [DWIDTH-1:0]`	Intended macro bit-write mask; undriven.
`sram_a_o`	output	`logic [AWIDTH-1:0]`	Intended macro read/write address; undriven.
`sram_di_o`	output	`logic [DWIDTH+PWIDTH-1:0]`	Intended macro write data including parity; undriven.
`sram_dout_i`	input	`logic [DWIDTH+PWIDTH-1:0]`	Intended macro read data including parity; unused.