sep_trng

Group the internal entropy source and DRBG under one local reset, rst_ni.

Owns:

entropy_source on a 32-bit AXI-Lite port (9-bit register offset), whose conditioned entropy stream seeds the DRBG directly.
The DRBG (CSRNG and EDN) on two 64-bit AXI-Lite ports, with NUM_AXIS EDN AXI-Stream endpoints and no native EDN endpoints.
CSRNG and EDN alerts; for each, index 0 is recoverable (recov_alert) and index 1 is fatal (fatal_alert).
Sticky CSRNG/EDN register-bridge faults, each held until its clear.

CSRNG software application reads are always enabled and lifecycle hardware debug is tied off. Source selection and consumer adapters live in sep_crypto because they also serve the external TRNG path.

trng_reset_active_o is rst_ni's assertion synchronized to clk_i under por_rst_ni; it is meant as a synchronous clear downstream, not as a reset.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_AXIS`	`int unsigned`	`sep_crypto_pkg::SepCryptoEdnEndpointCount`	Number of DRBG AXI-Stream endpoints; elaboration fails unless it equals SepCryptoEdnEndpointCount.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`por_rst_ni`	input	`logic`	Active-low power-on reset; resets only the trng_reset_active_o synchronizer.
`rst_ni`	input	`logic`	Active-low local reset for entropy_source and the DRBG.
`entropy_rosc_sample_clk_i`	input	`logic`	Ring-oscillator sample clock for entropy_source; asynchronous to clk_i.
`esrc_axil_req_i`	input	`sep_pkg::sep_32_32_axil_req_t`	entropy_source register request; address bits [8:0] are used.
`esrc_axil_resp_o`	output	`sep_pkg::sep_32_32_axil_resp_t`	entropy_source register response.
`csrng_axil_req_i`	input	`drbg_pkg::drbg_axil64_req_t`	CSRNG register request, bridged to TL-UL inside the DRBG.
`csrng_axil_resp_o`	output	`drbg_pkg::drbg_axil64_resp_t`	CSRNG register response.
`edn_axil_req_i`	input	`drbg_pkg::drbg_axil64_req_t`	EDN register request, bridged to TL-UL inside the DRBG.
`edn_axil_resp_o`	output	`drbg_pkg::drbg_axil64_resp_t`	EDN register response.
`drbg_axis_req_o`	output	`drbg_pkg::drbg_axis_req_t [NUM_AXIS-1:0]`	DRBG random-data streams, one independent stream per EDN endpoint.
`drbg_axis_rsp_i`	input	`drbg_pkg::drbg_axis_rsp_t [NUM_AXIS-1:0]`	Consumer tready for each DRBG random-data stream.
`csrng_alert_rx_i`	input	`prim_alert_pkg::alert_rx_t [csrng_reg_pkg::NumAlerts-1:0]`	CSRNG alert receiver handshakes; index 0 recoverable (recov_alert), index 1 fatal (fatal_alert).
`csrng_alert_tx_o`	output	`prim_alert_pkg::alert_tx_t [csrng_reg_pkg::NumAlerts-1:0]`	CSRNG differential alert senders; index 0 recoverable (recov_alert), index 1 fatal (fatal_alert).
`edn_alert_rx_i`	input	`prim_alert_pkg::alert_rx_t [edn_reg_pkg::NumAlerts-1:0]`	EDN alert receiver handshakes; index 0 recoverable (recov_alert), index 1 fatal (fatal_alert).
`edn_alert_tx_o`	output	`prim_alert_pkg::alert_tx_t [edn_reg_pkg::NumAlerts-1:0]`	EDN differential alert senders; index 0 recoverable (recov_alert), index 1 fatal (fatal_alert).
`entropy_source_irq_o`	output	`logic`	entropy_source interrupt, aggregating its sticky fault and health-test status.
`intr_cs_cmd_req_done_o`	output	`logic`	CSRNG command-request-done interrupt.
`intr_cs_entropy_req_o`	output	`logic`	CSRNG entropy-request interrupt.
`intr_cs_hw_inst_exc_o`	output	`logic`	CSRNG hardware-instance exception interrupt.
`intr_cs_fatal_err_o`	output	`logic`	CSRNG fatal-error interrupt.
`intr_edn_cmd_req_done_o`	output	`logic`	EDN command-request-done interrupt.
`intr_edn_fatal_err_o`	output	`logic`	EDN fatal-error interrupt.
`csrng_bus_err_o`	output	`logic`	Set by a TL-UL error response on the CSRNG register bridge; sticky until csrng_bus_err_clr_i.
`csrng_bus_err_clr_i`	input	`logic`	Single-cycle clear for csrng_bus_err_o, pulsed by PERIPH_BUS_ERR_CLEAR.csrng in sep.
`edn_bus_err_o`	output	`logic`	Set by a TL-UL error response on the EDN register bridge; sticky until edn_bus_err_clr_i.
`edn_bus_err_clr_i`	input	`logic`	Single-cycle clear for edn_bus_err_o, pulsed by PERIPH_BUS_ERR_CLEAR.edn in sep.
`trng_reset_active_o`	output	`logic`	High while rst_ni is asserted, through a two-flop synchronizer to clk_i that por_rst_ni resets high.