sep_wdt_wrap

Wrap the OpenTitan aon_timer watchdog with an AXI register interface.

The 64-bit AXI4 slave is downsized to 32 bits, rebased by subtracting the WDT base address, converted to AXI-Lite, and bridged to the aon_timer TL-UL port. clk_wdt_i times the bark and bite counters. rst_ni resets the register path; the SEP watchdog reset rst_wdt_ni resets the timer and its alert receivers, and rst_wdt_aon_clk_n is its copy synchronized into the clk_wdt_i domain. wdt_timer_rst_req_o is the watchdog request (bite); it holds until rst_wdt_ni asserts. wdt_alert_o aggregates the fatal alert pulse with integ_fail of all channels. wdt_debug_sleep_mode_i pauses the watchdog in debug sleep. RACL is compiled out, lifecycle escalation is tied off, and the wakeup timer outputs are unused.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	System clock.
`clk_wdt_i`	input	`logic`	Watchdog counter clock, asynchronous to clk_i; 200 kHz in sep.
`rst_ni`	input	`logic`	Active-low reset of the AXI to TL-UL register path.
`rst_wdt_ni`	input	`logic`	SEP watchdog reset, active-low: resets the timer and the alert receivers, and is synchronized into the clk_wdt_i domain.
`test_en_i`	input	`logic`	DFT test-enable (scan-enable).
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low; bypasses the reset synchronizer.
`sep_wdt_axi_req_i`	input	`sep_pkg::sep_32_64_6_12_axi_req_t`	64-bit AXI4 slave for the watchdog registers, at system addresses.
`sep_wdt_axi_resp_o`	output	`sep_pkg::sep_32_64_6_12_axi_resp_t`	Response on the watchdog register slave.
`intr_wdog_timer_bark_o`	output	`logic`	Watchdog bark interrupt; in sep, drives the SEP CPU non-maskable interrupt.
`wdt_timer_rst_req_o`	output	`logic`	Watchdog bite reset request, active-high, from the clk_wdt_i domain.
`wdt_alert_o`	output	`logic`	Aggregated fatal alert (alert pulse \| integ_fail of all channels).
`wdt_debug_sleep_mode_i`	input	`logic`	Sleep indication to the watchdog, which pauses while it is high if configured to pause in sleep.
`bus_err_o`	output	`logic`	Set by a TL-UL error response on the register bridge; sticky until bus_err_clr_i.
`bus_err_clr_i`	input	`logic`	Single-cycle clear for bus_err_o, pulsed by PERIPH_BUS_ERR_CLEAR.wdt in sep; a fault in the same cycle still latches.