EICG_wrapper
Gate clocks for Chipyard-generated SMC CPU designs.
Adapts prim_clock_gating to the EICG_wrapper port names Chipyard emits. test_en bypasses gating so scan and DFT can drive the clock freely; the generated cluster ties test_en low on every instance.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
in | input | logic | Clock input. |
test_en | input | logic | Active-high test enable; forces the clock on regardless of en. |
en | input | logic | Active-high clock enable; low holds out low. |
out | output | logic | Gated clock output. |