OCAH4CORECluster_Arbiter2_Valid_PTWReq

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`io_in_0_ready`	output		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_0_valid`	input		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_0_bits_bits_addr`	input	`[44:0]`	@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_0_bits_bits_need_gpa`	input		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_1_ready`	output		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_1_valid`	input		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_1_bits_valid`	input		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_1_bits_bits_addr`	input	`[44:0]`	@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_in_1_bits_bits_need_gpa`	input		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_out_ready`	input		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_out_valid`	output		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_out_bits_valid`	output		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_out_bits_bits_addr`	output	`[44:0]`	@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_out_bits_bits_need_gpa`	output		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]
`io_chosen`	output		@[src/main/scala/chisel3/util/Arbiter.scala:140:14]