OCAH4CORECluster_AsyncQueueSink_TLBundleA_a9d32s1k1z2u

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:136:7]
`reset`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:136:7]
`io_deq_ready`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_deq_valid`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_deq_bits_opcode`	output	`[2:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_deq_bits_size`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_deq_bits_source`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_deq_bits_address`	output	`[8:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_deq_bits_mask`	output	`[3:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_deq_bits_data`	output	`[31:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_mem_0_opcode`	input	`[2:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_mem_0_address`	input	`[8:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_mem_0_data`	input	`[31:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_ridx`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_widx`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_safe_ridx_valid`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_safe_widx_valid`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_safe_source_reset_n`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]
`io_async_safe_sink_reset_n`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:139:14]