OCAH4CORECluster_AsyncQueueSource_DebugInternalBundle

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:70:7]
`reset`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:70:7]
`io_enq_ready`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_valid`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_resumereq`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hartsel`	input	`[9:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_ackhavereset`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hasel`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hamask_0`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hamask_1`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hamask_2`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hamask_3`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hrmask_0`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hrmask_1`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hrmask_2`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_enq_bits_hrmask_3`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_resumereq`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hartsel`	output	`[9:0]`	@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_ackhavereset`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hasel`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hamask_0`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hamask_1`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hamask_2`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hamask_3`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hrmask_0`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hrmask_1`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hrmask_2`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_mem_0_hrmask_3`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_ridx`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_widx`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_safe_ridx_valid`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_safe_widx_valid`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_safe_source_reset_n`	output		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
`io_async_safe_sink_reset_n`	input		@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]