OCAH4CORECluster_AsyncQueueSource_TLBundleD_a9d32s1k1z2u

Generated by CIRCT.

Ports

Table 1. Ports
NameDirectionTypeDescription
clockinput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:70:7]
resetinput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:70:7]
io_enq_readyoutput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_enq_validinput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_enq_bits_opcodeinput[2:0]@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_enq_bits_sizeinput[1:0]@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_enq_bits_sourceinput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_enq_bits_datainput[31:0]@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_mem_0_opcodeoutput[2:0]@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_mem_0_sizeoutput[1:0]@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_mem_0_sourceoutput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_mem_0_dataoutput[31:0]@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_ridxinput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_widxoutput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_safe_ridx_validinput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_safe_widx_validoutput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_safe_source_reset_noutput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]
io_async_safe_sink_reset_ninput@[generators/rocket-chip/src/main/scala/util/AsyncQueue.scala:73:14]