OCAH4CORECluster_AsyncResetRegVec_w1_i0
Generated by CIRCT.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clock | input | | @[generators/rocket-chip/src/main/scala/util/AsyncResetReg.scala:56:7] |
reset | input | | @[generators/rocket-chip/src/main/scala/util/AsyncResetReg.scala:56:7] |
io_d | input | | @[generators/rocket-chip/src/main/scala/util/AsyncResetReg.scala:59:14] |
io_q | output | | @[generators/rocket-chip/src/main/scala/util/AsyncResetReg.scala:59:14] |
io_en | input | | @[generators/rocket-chip/src/main/scala/util/AsyncResetReg.scala:59:14] |