OCAH4CORECluster_AsyncResetSynchronizerShiftReg_w1_d3_i0_1
Generated by CIRCT.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clock | input | | @[generators/rocket-chip/src/main/scala/util/SynchronizerReg.scala:80:7] |
reset | input | | @[generators/rocket-chip/src/main/scala/util/SynchronizerReg.scala:80:7] |
io_d | input | | @[generators/rocket-chip/src/main/scala/util/ShiftReg.scala:36:14] |
io_q | output | | @[generators/rocket-chip/src/main/scala/util/ShiftReg.scala:36:14] |