OCAH4CORECluster_ClockCrossingReg_w21

Generated by CIRCT.

Ports

Table 1. Ports
NameDirectionTypeDescription
clockinput@[generators/rocket-chip/src/main/scala/util/SynchronizerReg.scala:191:7]
io_dinput[20:0]@[generators/rocket-chip/src/main/scala/util/SynchronizerReg.scala:195:14]
io_qoutput[20:0]@[generators/rocket-chip/src/main/scala/util/SynchronizerReg.scala:195:14]
io_eninput@[generators/rocket-chip/src/main/scala/util/SynchronizerReg.scala:195:14]