OCAH4CORECluster_DCacheDataArray

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`l1_dcache_data_arrays_0_req`	output	`chipyard_4core_mem_pkg::l1_dcache_data_req_t`
`l1_dcache_data_arrays_0_rsp`	input	`chipyard_4core_mem_pkg::l1_dcache_data_rsp_t`
`clock`	input		@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:49:7]
`io_req_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:50:14]
`io_req_bits_addr`	input	`[10:0]`	@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:50:14]
`io_req_bits_write`	input		@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:50:14]
`io_req_bits_wdata`	input	`[71:0]`	@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:50:14]
`io_req_bits_way_en`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:50:14]
`io_resp_0`	output	`[71:0]`	@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:50:14]
`io_resp_1`	output	`[71:0]`	@[generators/rocket-chip/src/main/scala/rocket/DCache.scala:50:14]