OCAH4CORECluster_Frontend

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`l1_icache_tag_array_req`	output	`chipyard_4core_mem_pkg::l1_icache_tag_req_t`
`l1_icache_tag_array_rsp`	input	`chipyard_4core_mem_pkg::l1_icache_tag_rsp_t`
`l1_icache_data_arrays_1_req`	output	`chipyard_4core_mem_pkg::l1_icache_data_req_t`
`l1_icache_data_arrays_1_rsp`	input	`chipyard_4core_mem_pkg::l1_icache_data_rsp_t`
`l1_icache_data_arrays_0_req`	output	`chipyard_4core_mem_pkg::l1_icache_data_req_t`
`l1_icache_data_arrays_0_rsp`	input	`chipyard_4core_mem_pkg::l1_icache_data_rsp_t`
`clock`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:82:7]
`reset`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:82:7]
`auto_icache_master_out_a_ready`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_a_valid`	output		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_a_bits_opcode`	output	`[2:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_a_bits_source`	output		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_a_bits_address`	output	`[55:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_d_valid`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_d_bits_opcode`	input	`[2:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_d_bits_size`	input	`[3:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_d_bits_denied`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_d_bits_data`	input	`[63:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_icache_master_out_d_bits_corrupt`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_reset_vector_sink_in`	input	`[55:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`io_cpu_might_request`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_clock_enabled`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_req_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_req_bits_pc`	input	`[57:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_req_bits_speculative`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_sfence_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_sfence_bits_rs1`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_sfence_bits_rs2`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_sfence_bits_addr`	input	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_ready`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_btb_taken`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_btb_bridx`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_btb_entry`	output	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_btb_bht_history`	output	`[7:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_pc`	output	`[57:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_data`	output	`[31:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_xcpt_pf_inst`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_xcpt_gf_inst`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_xcpt_ae_inst`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_resp_bits_replay`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_btb_update_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_btb_update_bits_prediction_entry`	input	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_btb_update_bits_pc`	input	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_btb_update_bits_isValid`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_btb_update_bits_br_pc`	input	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_btb_update_bits_cfiType`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_bht_update_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_bht_update_bits_prediction_history`	input	`[7:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_bht_update_bits_pc`	input	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_bht_update_bits_branch`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_bht_update_bits_taken`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_bht_update_bits_mispredict`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_flush_icache`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_perf_acquire`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_perf_tlbMiss`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_cpu_progress`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_req_ready`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_req_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_req_bits_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_req_bits_bits_addr`	output	`[44:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_req_bits_bits_need_gpa`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_ae_ptw`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_ae_final`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pf`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_gf`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_hr`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_hw`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_hx`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_ppn`	input	`[43:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_d`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_a`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_g`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_u`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_pte_v`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_level`	input	`[2:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_resp_bits_homogeneous`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_ptbr_mode`	input	`[3:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_status_debug`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_status_prv`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_0_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_0_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_0_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_0_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_0_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_0_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_0_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_1_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_1_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_1_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_1_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_1_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_1_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_1_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_2_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_2_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_2_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_2_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_2_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_2_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_2_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_3_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_3_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_3_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_3_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_3_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_3_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_3_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_4_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_4_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_4_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_4_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_4_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_4_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_4_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_5_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_5_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_5_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_5_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_5_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_5_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_5_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_6_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_6_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_6_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_6_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_6_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_6_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_6_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_7_cfg_l`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_7_cfg_a`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_7_cfg_x`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_7_cfg_w`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_7_cfg_r`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_7_addr`	input	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_pmp_7_mask`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_customCSRs_csrs_0_wen`	input		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_customCSRs_csrs_0_value`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_ptw_customCSRs_csrs_1_value`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_errors_correctable_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_errors_bus_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]
`io_errors_bus_bits`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/Frontend.scala:85:14]