OCAH4CORECluster_ICache

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`l1_icache_tag_array_req`	output	`chipyard_4core_mem_pkg::l1_icache_tag_req_t`
`l1_icache_tag_array_rsp`	input	`chipyard_4core_mem_pkg::l1_icache_tag_rsp_t`
`l1_icache_data_arrays_1_req`	output	`chipyard_4core_mem_pkg::l1_icache_data_req_t`
`l1_icache_data_arrays_1_rsp`	input	`chipyard_4core_mem_pkg::l1_icache_data_rsp_t`
`l1_icache_data_arrays_0_req`	output	`chipyard_4core_mem_pkg::l1_icache_data_req_t`
`l1_icache_data_arrays_0_rsp`	input	`chipyard_4core_mem_pkg::l1_icache_data_rsp_t`
`clock`	input		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:251:7]
`reset`	input		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:251:7]
`auto_master_out_a_ready`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_a_valid`	output		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_a_bits_opcode`	output	`[2:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_a_bits_source`	output		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_a_bits_address`	output	`[55:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_d_valid`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_d_bits_opcode`	input	`[2:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_d_bits_size`	input	`[3:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_d_bits_denied`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_d_bits_data`	input	`[63:0]`	@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`auto_master_out_d_bits_corrupt`	input		@[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25]
`io_req_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_req_bits_addr`	input	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_s1_paddr`	input	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_s1_kill`	input		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_s2_kill`	input		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_resp_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_resp_bits_data`	output	`[31:0]`	@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_resp_bits_replay`	output		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_resp_bits_ae`	output		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_invalidate`	input		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_errors_correctable_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_errors_bus_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_errors_bus_bits`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_perf_acquire`	output		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]
`io_keep_clock_enabled`	output		@[generators/rocket-chip/src/main/scala/rocket/ICache.scala:256:14]