OCAH4CORECluster_LevelGateway

Generated by CIRCT.

Ports

Table 1. Ports
NameDirectionTypeDescription
clockinput@[generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:31:7]
resetinput@[generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:31:7]
io_interruptinput@[generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:32:14]
io_plic_validoutput@[generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:32:14]
io_plic_readyinput@[generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:32:14]
io_plic_completeinput@[generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:32:14]