OCAH4CORECluster_MulDiv

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:40:7]
`reset`	input		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:40:7]
`io_req_ready`	output		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_req_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_req_bits_fn`	input	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_req_bits_dw`	input		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_req_bits_in1`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_req_bits_in2`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_req_bits_tag`	input	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_kill`	input		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_resp_ready`	input		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_resp_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_resp_bits_data`	output	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]
`io_resp_bits_tag`	output	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/Multiplier.scala:45:14]