OCAH4CORECluster_NonSyncResetSynchronizerPrimitiveShiftReg_d3

Replace the Chipyard non-sync reset shift-register black box.

Substitutes prim_flop_3sync, a three-flop synchronizer without reset, for the generated box. Preserves the three-stage depth the generated cluster expects.

Ports

Table 1. Ports
NameDirectionTypeDescription
clockinputDestination clock for the three synchronizer flops.
io_dData bit to synchronize into the clock domain.
io_qoutputData bit after three clock-domain flops; not reset.