OCAH4CORECluster_Queue1_AXI4BundleAR

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[src/main/scala/chisel3/util/Decoupled.scala:243:7]
`reset`	input		@[src/main/scala/chisel3/util/Decoupled.scala:243:7]
`io_enq_ready`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_valid`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_id`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_addr`	input	`[55:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_len`	input	`[7:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_size`	input	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_burst`	input	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_lock`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_cache`	input	`[3:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_prot`	input	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_qos`	input	`[3:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_echo_extra_id`	input	`[6:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_ready`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_valid`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_id`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_addr`	output	`[55:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_len`	output	`[7:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_size`	output	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_burst`	output	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_cache`	output	`[3:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_prot`	output	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_echo_extra_id`	output	`[6:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]