OCAH4CORECluster_Queue1_AXI4BundleW
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Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clock | input | | @[src/main/scala/chisel3/util/Decoupled.scala:243:7] |
reset | input | | @[src/main/scala/chisel3/util/Decoupled.scala:243:7] |
io_enq_ready | output | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_valid | input | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_bits_data | input | [63:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_bits_strb | input | [7:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_bits_last | input | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_ready | input | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_valid | output | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_bits_data | output | [63:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_bits_strb | output | [7:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_bits_last | output | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |