OCAH4CORECluster_Queue1_RegMapperInput_i23_m8

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[generators/rocket-chip/src/main/scala/regmapper/RegMapper.scala:71:32]
`reset`	input		@[generators/rocket-chip/src/main/scala/regmapper/RegMapper.scala:71:32]
`io_enq_ready`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_valid`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_read`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_index`	input	`[22:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_data`	input	`[63:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_mask`	input	`[7:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_extra_tlrr_extra_source`	input	`[12:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_extra_tlrr_extra_size`	input	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_ready`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_valid`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_read`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_index`	output	`[22:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_data`	output	`[63:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_mask`	output	`[7:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_extra_tlrr_extra_source`	output	`[12:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_extra_tlrr_extra_size`	output	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]