OCAH4CORECluster_Queue2_TLBundleA_a32d64s11k1z3u

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[src/main/scala/chisel3/util/Decoupled.scala:243:7]
`reset`	input		@[src/main/scala/chisel3/util/Decoupled.scala:243:7]
`io_enq_ready`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_valid`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_opcode`	input	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_param`	input	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_size`	input	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_source`	input	`[10:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_address`	input	`[31:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_mask`	input	`[7:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_data`	input	`[63:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_corrupt`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_ready`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_valid`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_opcode`	output	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_param`	output	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_size`	output	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_source`	output	`[10:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_address`	output	`[31:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_mask`	output	`[7:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_data`	output	`[63:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_corrupt`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]