OCAH4CORECluster_Queue3_BundleMap
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Ports
| Name | Direction | Type | Description |
|---|---|---|---|
clock | input | | @[src/main/scala/chisel3/util/Decoupled.scala:243:7] |
reset | input | | @[src/main/scala/chisel3/util/Decoupled.scala:243:7] |
io_enq_ready | output | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_valid | input | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_bits_tl_state_size | input | [3:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_bits_tl_state_source | input | [8:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_enq_bits_extra_id | input | [1:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_ready | input | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_valid | output | | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_bits_tl_state_size | output | [3:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_bits_tl_state_source | output | [8:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |
io_deq_bits_extra_id | output | [1:0] | @[src/main/scala/chisel3/util/Decoupled.scala:255:14] |