OCAH4CORECluster_Queue8_AXI4BundleR

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[src/main/scala/chisel3/util/Decoupled.scala:243:7]
`reset`	input		@[src/main/scala/chisel3/util/Decoupled.scala:243:7]
`io_enq_ready`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_valid`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_id`	input	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_data`	input	`[63:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_resp`	input	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_echo_tl_state_size`	input	`[3:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_echo_tl_state_source`	input	`[8:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_echo_extra_id`	input	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_enq_bits_last`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_ready`	input		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_id`	output	`[2:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_data`	output	`[63:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_resp`	output	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_echo_tl_state_size`	output	`[3:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_echo_tl_state_source`	output	`[8:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_echo_extra_id`	output	`[1:0]`	@[src/main/scala/chisel3/util/Decoupled.scala:255:14]
`io_deq_bits_last`	output		@[src/main/scala/chisel3/util/Decoupled.scala:255:14]