OCAH4CORECluster_Repeater_TLBundleA_a32d64s9k1z3u

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clock`	input		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:10:7]
`reset`	input		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:10:7]
`io_repeat`	input		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_full`	output		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_enq_ready`	output		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_enq_valid`	input		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_enq_bits_opcode`	input	`[2:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_enq_bits_size`	input	`[2:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_enq_bits_source`	input	`[8:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_enq_bits_address`	input	`[31:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_enq_bits_mask`	input	`[7:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_deq_ready`	input		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_deq_valid`	output		@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_deq_bits_opcode`	output	`[2:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_deq_bits_size`	output	`[2:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_deq_bits_source`	output	`[8:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_deq_bits_address`	output	`[31:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]
`io_deq_bits_mask`	output	`[7:0]`	@[generators/rocket-chip/src/main/scala/util/Repeater.scala:13:14]