OCAH4CORECluster_Rocket

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`o_wb_pc_valid`	output	`logic [1-1:0][1-1:0]`
`o_wb_reg_pc`	output	`logic [1-1:0][58-1:0]`
`clock`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:153:7]
`reset`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:153:7]
`io_hartid`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_interrupts_debug`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_interrupts_mtip`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_interrupts_msip`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_interrupts_meip`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_interrupts_seip`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_interrupts_buserror`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_might_request`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_req_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_req_bits_pc`	output	`[57:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_req_bits_speculative`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_sfence_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_sfence_bits_rs1`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_sfence_bits_rs2`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_sfence_bits_addr`	output	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_ready`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_btb_taken`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_btb_bridx`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_btb_entry`	input	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_btb_bht_history`	input	`[7:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_pc`	input	`[57:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_data`	input	`[31:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_xcpt_pf_inst`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_xcpt_gf_inst`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_xcpt_ae_inst`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_resp_bits_replay`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_btb_update_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_btb_update_bits_prediction_entry`	output	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_btb_update_bits_pc`	output	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_btb_update_bits_isValid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_btb_update_bits_br_pc`	output	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_btb_update_bits_cfiType`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_bht_update_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_bht_update_bits_prediction_history`	output	`[7:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_bht_update_bits_pc`	output	`[56:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_bht_update_bits_branch`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_bht_update_bits_taken`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_bht_update_bits_mispredict`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_flush_icache`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_perf_acquire`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_perf_tlbMiss`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_imem_progress`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_ready`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_bits_addr`	output	`[57:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_bits_tag`	output	`[6:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_bits_cmd`	output	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_bits_size`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_bits_signed`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_bits_dprv`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_req_bits_dv`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s1_kill`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s1_data_data`	output	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s2_nack`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_resp_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_resp_bits_tag`	input	`[6:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_resp_bits_size`	input	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_resp_bits_data`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_resp_bits_replay`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_resp_bits_has_data`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_resp_bits_data_word_bypass`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_replay_next`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s2_xcpt_ma_ld`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s2_xcpt_ma_st`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s2_xcpt_pf_ld`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s2_xcpt_pf_st`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s2_xcpt_ae_ld`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_s2_xcpt_ae_st`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_ordered`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_perf_acquire`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_perf_release`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_perf_grant`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_perf_tlbMiss`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_perf_blocked`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_keep_clock_enabled`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_dmem_clock_enabled`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_ptbr_mode`	output	`[3:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_ptbr_ppn`	output	`[43:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_sfence_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_sfence_bits_rs1`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_status_debug`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_status_prv`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_status_mxr`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_status_sum`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_0_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_0_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_0_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_0_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_0_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_0_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_0_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_1_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_1_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_1_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_1_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_1_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_1_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_1_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_2_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_2_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_2_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_2_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_2_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_2_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_2_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_3_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_3_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_3_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_3_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_3_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_3_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_3_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_4_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_4_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_4_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_4_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_4_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_4_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_4_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_5_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_5_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_5_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_5_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_5_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_5_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_5_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_6_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_6_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_6_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_6_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_6_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_6_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_6_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_7_cfg_l`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_7_cfg_a`	output	`[1:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_7_cfg_x`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_7_cfg_w`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_7_cfg_r`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_7_addr`	output	`[53:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_pmp_7_mask`	output	`[55:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_customCSRs_csrs_0_wen`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_customCSRs_csrs_0_value`	output	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_ptw_customCSRs_csrs_1_value`	output	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_inst`	output	`[31:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_fromint_data`	output	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_fcsr_rm`	output	`[2:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_fcsr_flags_valid`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_fcsr_flags_bits`	input	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_store_data`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_toint_data`	input	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_ll_resp_val`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_ll_resp_type`	output	`[2:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_ll_resp_tag`	output	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_ll_resp_data`	output	`[63:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_valid`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_fcsr_rdy`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_nack_mem`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_illegal_rm`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_killx`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_killm`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_ldst`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_wen`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_ren1`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_ren2`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_ren3`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_swap23`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_fma`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_div`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_dec_sqrt`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_sboard_set`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_sboard_clr`	input		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_sboard_clra`	input	`[4:0]`	@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_fpu_keep_clock_enabled`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_cease`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]
`io_wfi`	output		@[generators/rocket-chip/src/main/scala/rocket/RocketCore.scala:134:14]