OCAH4CORECluster_SynchronizerShiftReg_w328_d3

Generated by CIRCT.

Ports

Table 1. Ports
NameDirectionTypeDescription
clockinput@[generators/rocket-chip/src/main/scala/util/SynchronizerReg.scala:169:7]
io_dinput[327:0]@[generators/rocket-chip/src/main/scala/util/ShiftReg.scala:36:14]
io_qoutput[327:0]@[generators/rocket-chip/src/main/scala/util/ShiftReg.scala:36:14]