OCAH4CORECluster_TTTLDebugModule
Generated by CIRCT.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
auto_dmInner_dmInner_sb2tlOpt_out_a_ready | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_a_valid | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode | output | [2:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size | output | [3:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address | output | [55:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data | output | [7:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_ready | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_valid | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode | input | [2:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param | input | [1:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size | input | [3:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink | input | [1:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data | input | [7:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_ready | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_valid | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_bits_opcode | input | [2:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_bits_size | input | [1:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_bits_source | input | [12:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_bits_address | input | [31:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_bits_mask | input | [7:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_a_bits_data | input | [63:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_d_ready | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_d_valid | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_d_bits_opcode | output | [2:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_d_bits_size | output | [1:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_d_bits_source | output | [12:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmInner_dmInner_tl_in_d_bits_data | output | [63:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmOuter_int_out_3_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmOuter_int_out_2_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmOuter_int_out_1_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_dmOuter_int_out_0_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
io_debug_clock | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_debug_reset | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_tl_clock | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_tl_reset | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_ctrl_dmactive | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_ctrl_dmactiveAck | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_req_ready | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_req_valid | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_req_bits_addr | input | [6:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_req_bits_data | input | [31:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_req_bits_op | input | [1:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_resp_ready | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_resp_valid | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_resp_bits_data | output | [31:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmi_resp_bits_resp | output | [1:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmiClock | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_dmi_dmiReset | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartIsInReset_0 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartIsInReset_1 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartIsInReset_2 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartIsInReset_3 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartResetReq_0 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartResetReq_1 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartResetReq_2 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |
io_hartResetReq_3 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:146:16] |