OCAH4CORECluster_TTTLDebugModuleOuterAsync
Generated by CIRCT.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
auto_asource_out_a_mem_0_opcode | output | [2:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_mem_0_address | output | [8:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_mem_0_data | output | [31:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_ridx | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_widx | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_safe_ridx_valid | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_safe_widx_valid | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_safe_source_reset_n | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_a_safe_sink_reset_n | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_mem_0_opcode | input | [2:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_mem_0_size | input | [1:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_mem_0_source | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_mem_0_data | input | [31:0] | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_ridx | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_widx | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_safe_ridx_valid | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_safe_widx_valid | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_safe_source_reset_n | input | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_asource_out_d_safe_sink_reset_n | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_int_out_3_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_int_out_2_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_int_out_1_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
auto_int_out_0_sync_0 | output | | @[generators/diplomacy/diplomacy/src/diplomacy/lazymodule/LazyModuleImp.scala:107:25] |
io_dmi_clock | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_reset | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_req_ready | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_req_valid | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_req_bits_addr | input | [6:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_req_bits_data | input | [31:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_req_bits_op | input | [1:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_resp_ready | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_resp_valid | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_resp_bits_data | output | [31:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_dmi_resp_bits_resp | output | [1:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_ctrl_dmactive | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_ctrl_dmactiveAck | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_resumereq | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hartsel | output | [9:0] | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_ackhavereset | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hasel | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hamask_0 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hamask_1 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hamask_2 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hamask_3 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hrmask_0 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hrmask_1 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hrmask_2 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_mem_0_hrmask_3 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_ridx | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_widx | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_safe_ridx_valid | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_safe_widx_valid | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_safe_source_reset_n | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_innerCtrl_safe_sink_reset_n | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hgDebugInt_0 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hgDebugInt_1 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hgDebugInt_2 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hgDebugInt_3 | input | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hartResetReq_0 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hartResetReq_1 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hartResetReq_2 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |
io_hartResetReq_3 | output | | @[generators/chipyard/src/main/scala/tt_configs/TTDebug.scala:65:16] |