OCAH4CORECluster_mem_0

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type
`scratch_ram_req`	output	`chipyard_4core_mem_pkg::scratch_ram_req_t`
`scratch_ram_rsp`	input	`chipyard_4core_mem_pkg::scratch_ram_rsp_t`
`RW0_addr`	input	`[11:0]`
`RW0_en`	input
`RW0_clk`	input
`RW0_wmode`	input
`RW0_wdata`	input	`[71:0]`
`RW0_rdata`	output	`[71:0]`