OCAH4CORECluster_mems

Implement concrete memories for the four-core SMC cluster.

Builds ROM, scratch RAM, and L1 tag/data arrays behind the mem-swap structs. Forwards per-bank mem_cfg bits into each memory macro.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MEM_CFG_WIDTH`	`int`	`11`	Foundry memory config bus width.

Ports

Table 2. Ports
Name	Direction	Type	Description
`scratch_ram_req`	input	`chipyard_4core_mem_pkg::scratch_ram_req_t`	Scratch RAM requests from the cluster, one per bank; wmask is unused and writes cover the whole word.
`scratch_ram_rsp`	output	`chipyard_4core_mem_pkg::scratch_ram_rsp_t`	Scratch RAM read data returned to the cluster, one per bank.
`l1_icache_tag_req`	input	`chipyard_4core_mem_pkg::l1_icache_tag_req_t`	Instruction-cache tag array requests, one per bank.
`l1_icache_tag_rsp`	output	`chipyard_4core_mem_pkg::l1_icache_tag_rsp_t`	Instruction-cache tag array read data, one per bank.
`l1_icache_data_req`	input	`chipyard_4core_mem_pkg::l1_icache_data_req_t`	Instruction-cache data array requests, one per bank.
`l1_icache_data_rsp`	output	`chipyard_4core_mem_pkg::l1_icache_data_rsp_t`	Instruction-cache data array read data, one per bank.
`l1_dcache_tag_req`	input	`chipyard_4core_mem_pkg::l1_dcache_tag_req_t`	Data-cache tag array requests, one per bank.
`l1_dcache_tag_rsp`	output	`chipyard_4core_mem_pkg::l1_dcache_tag_rsp_t`	Data-cache tag array read data, one per bank.
`l1_dcache_data_req`	input	`chipyard_4core_mem_pkg::l1_dcache_data_req_t`	Data-cache data array requests, one per bank.
`l1_dcache_data_rsp`	output	`chipyard_4core_mem_pkg::l1_dcache_data_rsp_t`	Data-cache data array read data, one per bank.
`rom_req`	input	`chipyard_4core_mem_pkg::rom_req_t`	Boot ROM read request from the cluster ROM bridge.
`rom_rsp`	output	`chipyard_4core_mem_pkg::rom_rsp_t`	Boot ROM read data returned to the cluster ROM bridge.
`scratch_ram_cfg_i`	input	`logic [MEM_CFG_WIDTH-1:0]`	Foundry memory configuration for each scratch RAM bank macro.
`icache_tag_cfg_i`	input	`logic [MEM_CFG_WIDTH-1:0]`	Foundry memory configuration for each instruction-cache tag macro.
`icache_data_cfg_i`	input	`logic [MEM_CFG_WIDTH-1:0]`	Foundry memory configuration for each instruction-cache data macro.
`dcache_tag_cfg_i`	input	`logic [MEM_CFG_WIDTH-1:0]`	Foundry memory configuration for each data-cache tag macro.
`dcache_data_cfg_i`	input	`logic [MEM_CFG_WIDTH-1:0]`	Foundry memory configuration for each data-cache data macro.
`rom_cfg_i`	input	`logic [MEM_CFG_WIDTH-1:0]`	Foundry memory configuration for the boot ROM macro.