OCAH4CORECluster_ram_sink_2x2

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type	Description
`R0_addr`	input
`R0_en`	input
`R0_clk`	input
`R0_data`	output	`[1:0]`
`W0_addr`	input
`W0_en`	input
`W0_clk`	input
`W0_data`	input	`[1:0]`