OCAH4CORECluster_rockettile_dcache_data_arrays_0

Generated by CIRCT.

Ports

Table 1. Ports
Name	Direction	Type
`l1_dcache_data_arrays_0_req`	output	`chipyard_4core_mem_pkg::l1_dcache_data_req_t`
`l1_dcache_data_arrays_0_rsp`	input	`chipyard_4core_mem_pkg::l1_dcache_data_rsp_t`
`RW0_addr`	input	`[7:0]`
`RW0_en`	input
`RW0_clk`	input
`RW0_wmode`	input
`RW0_wdata`	input	`[143:0]`
`RW0_rdata`	output	`[143:0]`
`RW0_wmask`	input	`[1:0]`