smc

Integrate the System Management Controller chiplet top.

Instantiates reset, CPU, fabric, peripherals, and DFX under one SMC boundary. Bridges chiplet AXI ports, PLL clocks, powergood, and resets into smc_base and the peripheral domain. smc_base holds the fabric, internal registers, DFD and data accelerators; smc_cpu_wrapper holds the CPU cluster; smc_peripherals holds the peripherals, eFuse wrapper and reset unit. The ROM endianness bit comes from the eFuse shadow registers.

EFUSE_SHIM_SIZE is a literal carve-out at the base of the opaque smc_external window for the vendor eFuse shim CSR block; integrations that model the block override it. Memory-interface types are parameters rather than localparams so the mem-swap layer can specialize them.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MAX_TRANS`	`int unsigned`	`2`	Maximum outstanding transactions of the padring GPIO demux and of each GPIO interface.
`EFUSE_SHIM_SIZE`	`int unsigned`	`'h44`	Vendor eFuse shim CSR block carved off the base of the smc_external window. The open smc_external map is one opaque region, so this is a literal here and is overridden by an integration that models the block.
`NumCpuCores`	`int unsigned`	`smc_4core_cpu_pkg::NumCpuCores`	CPU cores in the SMC cluster; sizes the per-core writeback PC and watchdog timeout vectors.
`NumCpuInterrupts`	`int unsigned`	`smc_4core_cpu_pkg::NumCpuInterrupts`	Interrupt lines from smc_base to the CPU wrapper.
`NumExtInterrupts`	`int unsigned`	`smc_4core_cpu_pkg::NumExtInterrupts`	External interrupt lines accepted on smc_ext_interrupts_i.
`NumSramBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumSramBanks`	Scratch RAM banks; sizes the scratch RAM memory interface arrays.
`NumIcacheTagBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumIcacheTagBanks`	L1 instruction-cache tag banks; sizes the I-cache tag memory interface arrays.
`NumIcacheDataBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumIcacheDataBanks`	L1 instruction-cache data banks; sizes the I-cache data memory interface arrays.
`NumDcacheTagBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumDcacheTagBanks`	L1 data-cache tag banks; sizes the D-cache tag memory interface arrays.
`NumDcacheDataBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumDcacheDataBanks`	L1 data-cache data banks; sizes the D-cache data memory interface arrays.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_smc_i`	input	`logic`	SMC core clock for smc_base, the CPU wrapper and the SMC-clock peripherals.
`clk_ref_i`	input	`logic`	Reference clock for the reset unit, the CLA time tick, the CPU wrapper and the AVSBus controller.
`clk_periph_i`	input	`logic`	Peripheral clock for the UART, I2C, I3C and AVSBus register interfaces.
`powergood_i`	input	`logic`	Chip powergood from the pad, active-high; low asynchronously holds the reset unit's powergood stretcher and cold-reset de-glitcher in reset.
`powergood_stable_o`	output	`logic`	Powergood from the reset unit: falls with powergood_i and rises 32 reference clock cycles after it.
`rst_cold_ni`	input	`logic`	Cold reset, active-low, deglitched and extended in the reset unit.
`rst_cold_stable_ref_clk_no`	output	`logic`	De-glitched and extended cold reset, active-low, synchronized to the reference clock.
`rst_primary_ref_clk_no`	output	`logic`	Primary reset (cold, cool and function-level reset combined), active-low, synchronized to the reference clock.
`rst_primary_smc_clk_no`	output	`logic`	Primary reset, active-low, synchronized to the SMC clock; also resets smc_base and the CPU wrapper.
`rst_primary_periph_clk_no`	output	`logic`	Primary reset, active-low, synchronized to the peripheral clock.
`rst_wdt_smc_clk_no`	output	`logic`	Watchdog reset from the SEP watchdog or the second-stage SMC watchdog timeout, active-low, synchronized to the SMC clock.
`gated_clk_periph_i3c_o`	output	`logic`	Peripheral clock after the I3C clock gate; the clock of the I3C controllers.
`sys_axi_in_req_i`	input	`smc_pkg::smc_sys_in_56_64_6_12_axi_req_t`	Inbound system AXI request; passes the inbound filters to SMC local targets.
`sys_axi_in_resp_o`	output	`smc_pkg::smc_sys_in_56_64_6_12_axi_resp_t`	Inbound system AXI response.
`jtag_axi_in_req_i`	input	`smc_pkg::smc_jtag_56_64_2_12_axi_req_t`	JTAG debug AXI request, routed to SMC local targets or the output AXI port.
`jtag_axi_in_resp_o`	output	`smc_pkg::smc_jtag_56_64_2_12_axi_resp_t`	JTAG debug AXI response.
`axil_smc_otp_jtag_req_i`	input	`smc_pkg::smc_axil_32_32_req_t`	JTAG request into the eFuse wrapper, filtered by lifecycle state.
`axil_smc_otp_jtag_resp_o`	output	`smc_pkg::smc_axil_32_32_resp_t`	Response to the JTAG eFuse access path.
`sep_axi_in_req_i`	input	`smc_pkg::smc_sep_in_56_64_6_12_axi_req_t`	Inbound SEP AXI request, routed to SMC local targets.
`sep_axi_in_resp_o`	output	`smc_pkg::smc_sep_in_56_64_6_12_axi_resp_t`	Inbound SEP AXI response.
`output_axi_req_o`	output	`smc_pkg::smc_sys_out_56_64_8_12_axi_req_t`	Outbound AXI request from the output fabric, after the output remap and outbound filters.
`output_axi_resp_i`	input	`smc_pkg::smc_sys_out_56_64_8_12_axi_resp_t`	Outbound AXI response into the output fabric.
`axil_dtp_csr_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	DTP CSR request with its address rebased to zero at the DTP control window.
`axil_dtp_csr_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	DTP CSR response.
`shadow_regs_o`	output	`smc_efuse_pkg::efuse_map_t`	eFuse shadow-register contents; all zero until fuse sensing completes unless SEP security disable is set.
`smc_external_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	AXI-L interface for adopter peripheral request, covering the smc_external window above the eFuse shim carve-out.
`smc_external_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	Response from the adopter peripherals in the smc_external window.
`efuse_bank_ctrl_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	Request to the vendor eFuse shim CSRs.
`efuse_bank_ctrl_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	Response from the vendor eFuse shim CSRs.
`efuse_shim_command_req_o`	output	`smc_efuse_pkg::fuse_command_req_t`	Fuse sense and program command request to the shim state machine.
`efuse_shim_command_resp_i`	input	`smc_efuse_pkg::fuse_command_resp_t`	Fuse command response from the shim state machine.
`lsio_interface_select_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	LSIO select per pad, high where a peripheral function claims the pad.
`pad2core_i`	input	`logic [smc_pkg::NumGpioWraps-1:0]`	Value received from each GPIO pad.
`core2pad_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Value driven onto each GPIO pad.
`pad2core_en_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Input enable of each GPIO pad.
`core2pad_en_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Output enable of each GPIO pad.
`rst_cool_n_from_pin_i`	input	`logic`	Cool reset from the external pin, active-low; deglitched in the reset unit into the primary reset.
`spi_enable_i`	input	`logic`	Hands the SPI pads to the external SPI host, active-high.
`spi_clk_i`	input	`logic`	Serial clock from the external SPI host, driven onto the SPI clock pad.
`spi_txd_i`	input	`logic [7:0]`	Transmit data from the external SPI host, one bit per data pad.
`spi_cs_n_i`	input	`logic`	Chip select from the external SPI host, active-low.
`spi_cs_oe_n_i`	input	`logic`	Output enable for the chip-select pad, active-low.
`spi_cs_ie_n_i`	input	`logic`	Input enable for the chip-select pad, active-low.
`spi_clk_ie_n_i`	input	`logic`	Input enable for the SPI clock pad, active-low.
`spi_clk_oe_n_i`	input	`logic`	Output enable for the SPI clock pad, active-low.
`spi_dqs_ie_n_i`	input	`logic`	Input enable for the data-strobe pad, active-low.
`spi_dqs_oe_n_i`	input	`logic`	Output enable for the data-strobe pad, active-low; the pad drives zero when enabled.
`spi_dq_ie_n_i`	input	`logic [7:0]`	Input enables for the data pads, active-low, one bit per data pad.
`spi_dq_oe_n_i`	input	`logic [7:0]`	Output enables for the data pads, active-low, one bit per data pad.
`spi_rxd_o`	output	`logic [7:0]`	Receive data sampled from the data pads, to the external SPI host.
`spi_rxds_o`	output	`logic`	Read data strobe sampled from the data-strobe pad, used in DDR mode.
`spi_mem_rebar_oepad_i`	input	`logic`	Output enable for the SPI DQS loopback pad, active-high.
`spi_mem_rebar_opad_i`	input	`logic`	Data driven onto the SPI DQS loopback pad.
`spi_mem_rebar_iepad_i`	input	`logic`	Input enable for the SPI DQS loopback pad, active-high.
`spi_mem_rebar_ipad_o`	output	`logic`	Value sampled from the SPI DQS loopback pad.
`clk_telemetry_i`	input	`logic`	Telemetry clock for the ATB inputs, gated by the telemetry clock-gate enable.
`rst_telemetry_ni`	input	`logic`	Telemetry-domain reset, active-low, for the telemetry receivers' ATB FIFOs.
`telemetry_atdata_i`	input	`telemetry_receiver_pkg::telemetry_data_t [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB telemetry data, one word per receiver, on the telemetry clock.
`telemetry_atid_i`	input	`telemetry_receiver_pkg::atb_id_t [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB source ID accompanying each telemetry data word.
`telemetry_atready_o`	output	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB ready from each telemetry receiver to its source.
`telemetry_atvalid_i`	input	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB valid from each telemetry source.
`telemetry_afvalid_o`	output	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB flush request from each telemetry receiver to its source.
`telemetry_afready_i`	input	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB flush acknowledge from each telemetry source.
`smc_cluster_ded_o`	output	`logic`	Uncorrectable (double-error-detected) memory error from the SMC CPU cluster, registered on the SMC clock.
`smc_wdt_first_timeout_o`	output	`logic`	First-stage watchdog timeout: OR of the per-core CPU watchdog timeouts.
`smc_wdt_second_timeout_o`	output	`logic`	Second-stage watchdog timeout from the CPU control block, registered on the SMC clock; asserts the watchdog reset in the reset unit.
`smc_global_base_o`	output	`smc_pkg::smc_axi_addr_t`	SMC global base address from the smc_base configuration registers.
`smc_region_size_o`	output	`logic [31:0]`	SMC region size in bytes from the smc_base REGION_SIZE register.
`smc_ext_interrupts_i`	input	`logic [NumExtInterrupts-1:0]`	External interrupts, synchronized in smc_base onto the lowest CPU interrupt lines.
`sep_mailbox_interrupts_i`	input	`logic [7:0]`	SEP mailbox interrupts, placed on peripheral interrupt bits 7:0.
`sep_wdt_reset_n_i`	input	`logic`	SEP watchdog reset, active-low; drives the watchdog reset in the reset unit and a peripheral interrupt.
`smc_fuse_sense_done_o`	output	`logic`	High once eFuse sensing into the shadow registers completes; used to sequence MBIST and memory repair.
`smc_fuse_reset_n_delayed_o`	output	`logic`	Fuse-released reset, active-low, delayed by 16 SMC clock pipeline stages; held low while boot stall is asserted.
`skip_mem_repair_o`	output	`logic`	Asserted during a function-level reset to skip memory repair and MBIST.
`ext_boot_seq_done_i`	input	`logic`	External boot sequence done, active-high; the fuse-released reset stays low until it is set.
`ext_boot_seq_done_qual_o`	output	`logic`	ext_boot_seq_done_i synchronized to the SMC clock and held set until cold reset.
`sep_security_disable_i`	input	`logic`	Security disable from the SEP eFuse controller, active-high; skips automatic fuse sensing and releases the shadow registers without it.
`lc_state_i`	input	`logic [2*smc_pkg::LcStateWidth-1:0]`	Differentially encoded lifecycle state, used by the eFuse JTAG access filter and reported in chip_config.
`lc_sigint_err_o`	output	`logic`	Integrity error from the differential decode of lc_state_i, active-high.
`smc_ndmreset_request_i`	input	`logic [smc_config_pkg::CpuClusterCount - 1:0]`	Asynchronous NDM reset request from each external CPU cluster; raised as a peripheral interrupt.
`smc_ndmreset_process_o`	output	`logic [smc_config_pkg::CpuClusterCount - 1:0]`	Firmware response to each cluster's NDM reset request, from the NDMRESET_PROCESS register.
`smc_ext_mailbox_interrupts_o`	output	`logic [smc_pkg::NumMailboxes-1:0]`	Outbound interrupts of the SMC mailboxes, one per mailbox.
`cfg_flr_pf_active_i`	input	`logic`	PCIe function-level reset request, active-high; starts the reset unit's isolation and cool reset sequence.
`isolate_req_o`	output	`logic [31:0]`	Per-subsystem isolation requests from the reset unit.
`ss_reset_complete_i`	input	`logic [31:0]`	Per-subsystem reset complete acknowledgments, synchronized to the SMC clock in the reset unit.
`ss_config_o`	output	`logic [31:0]`	Per-subsystem configuration bits written through the reset-unit SS_CONFIG register; cleared by primary reset.
`ss_reset_ctrl_o`	output	`smc_reset_unit_pkg::reset_ctrl_t`	Per-subsystem cold and warm resets, hold controls and force-to-reference-clock select; the resets are not synchronized to the subsystem clock.
`sync_irq_o`	output	`logic`	Global sync bit set by software through the reset-unit SYNC_REG register.
`smc_rom_intf_req_o`	output	`rom_req_t`	Boot ROM read request from the CPU wrapper.
`smc_rom_intf_rsp_i`	input	`rom_rsp_t`	Boot ROM read data.
`smc_scratch_ram_intf_req_o`	output	`scratch_ram_req_t`	Scratch RAM bank requests, driven by the zero-fill until it completes.
`smc_scratch_ram_intf_rsp_i`	input	`scratch_ram_rsp_t`	Scratch RAM bank read data.
`smc_l1_icache_tag_intf_req_o`	output	`l1_icache_tag_req_t`	Instruction-cache tag bank requests.
`smc_l1_icache_tag_intf_rsp_i`	input	`l1_icache_tag_rsp_t`	Instruction-cache tag bank read data.
`smc_l1_icache_data_intf_req_o`	output	`l1_icache_data_req_t`	Instruction-cache data bank requests.
`smc_l1_icache_data_intf_rsp_i`	input	`l1_icache_data_rsp_t`	Instruction-cache data bank read data.
`smc_l1_dcache_tag_intf_req_o`	output	`l1_dcache_tag_req_t`	Data-cache tag bank requests.
`smc_l1_dcache_tag_intf_rsp_i`	input	`l1_dcache_tag_rsp_t`	Data-cache tag bank read data.
`smc_l1_dcache_data_intf_req_o`	output	`l1_dcache_data_req_t`	Data-cache data bank requests.
`smc_l1_dcache_data_intf_rsp_i`	input	`l1_dcache_data_rsp_t`	Data-cache data bank read data.
`smc_disable_sram_auto_init_i`	input	`logic`	Skips zeroing of the scratch RAM after reset, active-high.
`smc_init_mem_done_o`	output	`logic`	High once scratch RAM zeroing completes or is skipped.
`chiplet_is_primary_i`	input	`logic`	High on the primary chiplet: the system timer drives the timer sync pads, and the CPU wrapper reports it in SMC_ATTRIBUTES.
`timer_count_o`	output	`logic [63:0]`	Live 64-bit system timer count.
`boot_stall_jtag_ovrd_i`	input	`logic`	Replaces the boot-stall pad value with boot_stall_jtag_val_i when high.
`boot_stall_jtag_val_i`	input	`logic`	Boot-stall value used while the JTAG override is set.
`boot_stall_combined_o`	output	`logic`	Boot stall synchronized to the SMC clock and made sticky: once low it stays low until the next primary reset.
`jtag_reset_ctrl_i`	input	`smc_pkg::jtag_smc_reset_ctrl_t`	JTAG override selects and values for the fuse, cold, cool, warm and per-subsystem resets.
`cla_ext_action_custom_o`	output	`logic [cla_pkg::CLA_NUMBER_OF_CUSTOM_ACTIONS-1:0]`	Custom CLA external-action outputs, one bit per action.
`xtrigger_ss_o`	output	`smc_pkg::xtrigger_t`	Cross-trigger lanes from the SMC core logic analyzer to the subsystem cross-trigger matrix, masked by the clock-halt trigger mask.
`xtrigger_ss_i`	input	`smc_pkg::xtrigger_t`	Cross-trigger lanes from the subsystem cross-trigger matrix into the SMC core logic analyzer.
`tdr_dbg_ctrl_clock_stop_en_i`	input	`logic`	Enables reporting a CLA halt-clock action as a clock stop.
`tdr_dbg_ctrl_clocks_stopped_by_cla_o`	output	`logic`	High while an enabled CLA halt-clock action requests a clock stop.
`trace_mem_req_o`	output	`trace_mem_pkg::SinkMemPktIn_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Requests from the DFD trace sink to the external trace RAMs.
`trace_mem_resp_i`	input	`trace_mem_pkg::SinkMemPktOut_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Read data from the external trace RAMs.
`ext_debug_bus_i`	input	`logic [511:0]`	Adopter debug signals for the upper half of the SMC debug bus. Note: Ensure signals are 16-bit aligned within this bus.
`test_en_i`	input	`logic`	DFT test-mode enable, active-high; bypasses the clock gates and selects the scan reset.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low, used in place of functional resets while test_en_i is high.
`mem_repair_done_i`	input	`logic`	Memory repair has finished; reported in the DFX STATUS_SMU register.
`mem_repair_success_i`	input	`logic`	Memory repair succeeded; reported in the DFX STATUS_SMU register.
`mem_repair_abort_i`	input	`logic`	Memory repair was aborted; reported in the DFX STATUS_SMU register.
`mbist_done_i`	input	`logic`	Memory BIST has finished; reported in the DFX STATUS_SMU register.
`mbist_pass_i`	input	`logic`	Memory BIST passed; reported in the DFX STATUS_SMU register.
`mbist_abort_i`	input	`logic`	Memory BIST was aborted; reported in the DFX STATUS_SMU register.
`smc_cpu_jtag_TCK_i`	input	`logic`	JTAG test clock for the CPU cluster debug transport module.
`smc_cpu_jtag_TMS_i`	input	`logic`	JTAG test mode select for the CPU cluster debug transport module.
`smc_cpu_jtag_TDI_i`	input	`logic`	JTAG test data into the CPU cluster debug transport module.
`smc_cpu_jtag_TDO_data_o`	output	`logic`	JTAG test data out of the CPU cluster debug transport module.
`smc_cpu_jtag_reset_i`	input	`logic`	Active-high asynchronous reset of the CPU cluster JTAG TAP and debug module interface.
`smc_cpu_jtag_mfr_id_i`	input	`logic [10:0]`	Manufacturer ID reported in the CPU cluster JTAG IDCODE.
`smc_cpu_jtag_part_number_i`	input	`logic [15:0]`	Part number reported in the CPU cluster JTAG IDCODE.
`smc_cpu_jtag_version_i`	input	`logic [3:0]`	Version reported in the CPU cluster JTAG IDCODE.
`i3c_dat_mem_src_i`	input	`i3c_pkg::dat_mem_src_t [smc_config_pkg::NumI3c-1:0]`	Read data from each I3C device address table memory.
`i3c_dat_mem_sink_o`	output	`i3c_pkg::dat_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	Request to each I3C device address table memory.
`i3c_dct_mem_src_i`	input	`i3c_pkg::dct_mem_src_t [smc_config_pkg::NumI3c-1:0]`	Read data from each I3C device characteristics table memory.
`i3c_dct_mem_sink_o`	output	`i3c_pkg::dct_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	Request to each I3C device characteristics table memory.
`i3c_rlt_mem_src_i`	input	`i3c_pkg::rlt_mem_src_t [smc_config_pkg::NumI3c-1:0]`	Read data from each I3C reverse-lookup table memory.
`i3c_rlt_mem_sink_o`	output	`i3c_pkg::rlt_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	Request to each I3C reverse-lookup table memory.
`gpio_interrupt_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Interrupt from each GPIO interface, active-high, in the SMC clock domain.
`uart_interrupt_o`	output	`logic [smc_config_pkg::NumUart-1:0]`	UART interrupt from each UART on the peripheral clock, excluding UART error and log-engine interrupts.