smc_4core_cpu

Instantiate the four-core SMC Rocket CPU cluster shell.

Instantiates the Chipyard-generated OCAH4CORECluster_DigitalTop and the boundary logic around it: AXI isolation of the L2-frontend and MMIO ports with status clamping, a debug-module clock gate, core reset sequencing, scratch RAM zero-fill and a registered uncorrectable-error flag. Exposes TileLink/AXI cluster ports and interrupt inputs to smc_cpu_wrapper.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	Cluster clock for the core, uncore and debug domains and the boundary logic.
`rst_isolate_ni`	input	`logic`	Active-low reset for the L2-frontend and MMIO AXI isolate modules.
`mem_init_reset_ni`	input	`logic`	Active-low reset for the scratch RAM zero-fill sequencer; its release starts the zero-fill.
`rst_uncore_ni`	input	`logic`	Active-low cluster uncore reset; while low, the cluster boundary stays isolated and cluster_ded_o is cleared.
`rst_core_ni`	input	`logic [smc_4core_cpu_pkg::NumCpuCores-1:0]`	Active-low per-core reset; the core also stays in reset until the scratch RAM zero-fill completes and while the cluster requests a hart reset.
`rst_debug_ni`	input	`logic`	Active-low reset for the debug module and its clock-gate enable.
`isolate_req_i`	input	`logic`	Drain request for a software reset; while high, the cluster boundary is isolated and the status outputs are clamped.
`drained_o`	output	`logic`	High once both the L2-frontend and MMIO AXI isolate modules report isolated.
`isolate_flush_i`	input	`logic`	Flush request to both AXI isolate modules, latched until de-isolation; clears their outstanding-transaction state so isolation can complete.
`reset_vector_i`	input	`logic [smc_4core_cpu_pkg::NumCpuCores-1:0][55:0]`	Per-core boot address into the cluster.
`interrupts_i`	input	`logic [smc_4core_cpu_pkg::NumCpuInterrupts-1:0]`	Cluster interrupt lines, passed unchanged to DigitalTop.
`mmio_axi_req_o`	output	`smc_pkg::smc_cpu_mmio_axi_req_t`	Cluster MMIO AXI master request through the MMIO isolate module, with AxCACHE modifiable forced set; while isolated, the module answers the cluster with SLVERR.
`mmio_axi_resp_i`	input	`smc_pkg::smc_cpu_mmio_axi_resp_t`	Cluster MMIO AXI master response from the fabric.
`l2_frontend_axi_req_i`	input	`smc_pkg::smc_cpu_l2_frontend_axi_req_t`	AXI request into the cluster L2 frontend bus through its isolate module, which blocks rather than terminates while isolated.
`l2_frontend_axi_resp_o`	output	`smc_pkg::smc_cpu_l2_frontend_axi_resp_t`	AXI response from the cluster L2 frontend bus.
`smc_cpu_jtag_TCK_i`	input	`logic`	JTAG test clock for the cluster debug transport module.
`smc_cpu_jtag_TMS_i`	input	`logic`	JTAG test mode select for the cluster debug transport module.
`smc_cpu_jtag_TDI_i`	input	`logic`	JTAG test data into the cluster debug transport module.
`smc_cpu_jtag_TDO_data_o`	output	`logic`	JTAG test data out of the cluster debug transport module.
`smc_cpu_jtag_reset_i`	input	`logic`	Active-high asynchronous reset of the cluster JTAG debug transport module (TAP) and of the debug module's DMI interface.
`smc_cpu_jtag_mfr_id_i`	input	`logic [10:0]`	Manufacturer ID reported in the cluster JTAG IDCODE.
`smc_cpu_jtag_part_number_i`	input	`logic [15:0]`	Part number reported in the cluster JTAG IDCODE.
`smc_cpu_jtag_version_i`	input	`logic [3:0]`	Version reported in the cluster JTAG IDCODE.
`cluster_ded_o`	output	`logic`	Registered OR of the cluster's uncorrectable-error flags.
`wb_pc_valid_o`	output	`logic [smc_4core_cpu_pkg::NumCpuCores-1:0][1-1:0]`	Per-core qualifier for wb_reg_pc_o, forced low while the cluster boundary is isolated.
`wb_reg_pc_o`	output	`logic [smc_4core_cpu_pkg::NumCpuCores-1:0][58-1:0]`	Per-core writeback program counter, forced to zero while the cluster boundary is isolated.
`wdt_reset_o`	output	`logic [smc_4core_cpu_pkg::NumCpuCores-1:0]`	Per-core watchdog timeout from the cluster, forced low while the cluster boundary is isolated.
`rom_intf_req_o`	output	`chipyard_4core_mem_pkg::rom_tilelink_req_t`	TileLink A-channel request, D-channel ready, clock and reset from the cluster boot ROM port.
`rom_intf_rsp_i`	input	`chipyard_4core_mem_pkg::rom_tilelink_rsp_t`	TileLink A-channel ready and D-channel response to the cluster boot ROM port.
`scratch_ram_intf_req_o`	output	`chipyard_4core_mem_pkg::scratch_ram_req_t`	Scratch RAM bank requests, driven by the zero-fill sequencer until the zero-fill completes.
`scratch_ram_intf_rsp_i`	input	`chipyard_4core_mem_pkg::scratch_ram_rsp_t`	Scratch RAM bank read data.
`l1_icache_tag_intf_req_o`	output	`chipyard_4core_mem_pkg::l1_icache_tag_req_t`	Instruction-cache tag bank requests.
`l1_icache_tag_intf_rsp_i`	input	`chipyard_4core_mem_pkg::l1_icache_tag_rsp_t`	Instruction-cache tag bank read data.
`l1_icache_data_intf_req_o`	output	`chipyard_4core_mem_pkg::l1_icache_data_req_t`	Instruction-cache data bank requests.
`l1_icache_data_intf_rsp_i`	input	`chipyard_4core_mem_pkg::l1_icache_data_rsp_t`	Instruction-cache data bank read data.
`l1_dcache_tag_intf_req_o`	output	`chipyard_4core_mem_pkg::l1_dcache_tag_req_t`	Data-cache tag bank requests.
`l1_dcache_tag_intf_rsp_i`	input	`chipyard_4core_mem_pkg::l1_dcache_tag_rsp_t`	Data-cache tag bank read data.
`l1_dcache_data_intf_req_o`	output	`chipyard_4core_mem_pkg::l1_dcache_data_req_t`	Data-cache data bank requests.
`l1_dcache_data_intf_rsp_i`	input	`chipyard_4core_mem_pkg::l1_dcache_data_rsp_t`	Data-cache data bank read data.
`disable_sram_auto_init_i`	input	`logic`	High skips the scratch RAM zero-fill after mem_init_reset_ni releases.
`init_mem_done_o`	output	`logic`	High once the scratch RAM zero-fill has completed or been skipped.
`test_en_i`	input	`logic`	Scan test mode enable for the debug clock gate.