smc_cpu_ctrl_wrap

Wrap CPU control CSRs for the SMC cluster.

Implements the cpu_ctrl registers behind an AXI-Lite port: core, uncore and debug reset control with a drain handshake and timeout, per-core reset vectors and reset pulses, a second watchdog stage, an eight-entry writeback PC history per core, the reference counter, mutexes, semaphores, scratch registers and SMC_ATTRIBUTES. In smc_cpu_wrapper it sits behind the front-port demux beside the L2 frontend.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NO_ADDR_REMAP`	`bit`	`1'b1`	Reported in SMC_ATTRIBUTES.no_output_remap; no other effect in this module.
`NUM_CPU_CORES`	`int unsigned`	`4`	Number of CPU cores this block drives resets, reset vectors and watchdog counters for; at most MaxCPUCores.
`MaxCPUCores`	`int unsigned`	`4`	Number of cores the cpu_ctrl register map provides per-core fields for; sizes the internal per-core arrays.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_ref_i`	input	`logic`	Reference clock for the free-running REFERENCE_COUNTER counter.
`clk_smc_i`	input	`logic`	SMC core clock for the CSR block, reset control and watchdog logic.
`rst_warm_smc_clk_ni`	input	`logic`	Active-low warm reset in the clk_smc_i domain; while low, holds the core and uncore resets asserted and drives core_reset_vector_o to the default boot address 0xC0040000.
`rst_primary_ni`	input	`logic`	Active-low primary reset in the clk_smc_i domain; resets the CSR block, reference counter, watchdog, PC history, reset-control state, mutexes and semaphores.
`test_en_i`	input	`logic`	Scan test mode enable; not used in this module.
`scan_rst_ni`	input	`logic`	Active-low scan reset; not used in this module.
`axil_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	AXI-Lite request to the cpu_ctrl CSR block from the SMC front-port demux.
`axil_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	AXI-Lite response from the cpu_ctrl CSR block.
`wb_reg_pc_i`	input	`logic [NUM_CPU_CORES-1:0][57:0]`	Per-core writeback program counter from the cluster, sampled on clk_smc_i into the eight-entry WB_PC_CORE history; a value equal to the newest entry is not added again.
`wb_pc_valid_i`	input	`logic [NUM_CPU_CORES-1:0]`	Per-core qualifier for wb_reg_pc_i; a new PC enters the history only while this is high.
`wdt_timeout_cluster_i`	input	`logic [NUM_CPU_CORES-1:0]`	Per-core first-stage watchdog timeout; while high, that core's second-stage counter counts down, and while low it reloads from WDT_TIMEOUT.
`chiplet_is_primary_i`	input	`logic`	High on the primary chiplet; read back through SMC_ATTRIBUTES.
`wdt_second_timeout_o`	output	`logic`	Registered second-stage watchdog timeout; high while any core's counter is zero.
`core_reset_n_n0_scan_o`	output	`logic [NUM_CPU_CORES-1:0]`	Active-low per-core reset from RESET_CTRL or a reset pulse, registered on clk_smc_i and low while warm reset is asserted; a software assertion waits for the cluster to drain or, in timeout mode, for the RESET_TIMEOUT timeout.
`core_reset_vector_o`	output	`logic [NUM_CPU_CORES-1:0][55:0]`	Per-core boot address from the RESET_VECTOR registers; the default boot address while warm reset is asserted.
`cluster_uncore_reset_n_n0_scan_o`	output	`logic`	Active-low uncore reset from RESET_CTRL, registered on clk_smc_i and low while warm reset is asserted; a software assertion waits for the cluster to drain or, in timeout mode, for the RESET_TIMEOUT timeout.
`debug_reset_n_o`	output	`logic`	Active-low debug-module reset, driven directly from the RESET_CTRL debug reset field, which resets to 0 (asserted); not held by the drain handshake.
`isolate_req_o`	output	`logic`	Drain request to the cluster: high while RESET_CTRL holds a core or the uncore in reset, or a core reset pulse is pending or in flight.
`drained_i`	input	`logic`	High once the cluster boundary has drained and isolated; releases a withheld software reset.
`isolate_flush_o`	output	`logic`	Flush request to the cluster AXI isolate modules, high while the RESET_TIMEOUT timeout forces a withheld reset in timeout mode.