smc_cpu_wrapper

Wrap the four-core SMC CPU cluster with its cpu_ctrl register block and boot ROM bridge.

Splits the fabric AXI front port by address between the cluster L2 frontend and cpu_ctrl, which it reaches through an AXI-to-AXI-Lite converter; the cluster MMIO master goes back out. Surfaces per-core PC, WDT, and cluster error status back to smc_base. Converts the cluster boot ROM TileLink port to the ROM memory interface, and exposes the scratch RAM and L1 cache bank interfaces; the memories themselves are outside this module.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NO_ADDR_REMAP`	`bit`	`1'b1`	Reported by cpu_ctrl in SMC_ATTRIBUTES.no_output_remap; no other effect in this module.
`NumCpuCores`	`int unsigned`	`smc_4core_cpu_pkg::NumCpuCores`	Number of cores in the cluster, from smc_4core_cpu_pkg; sizes the per-core PC and watchdog ports.
`NumCpuInterrupts`	`int unsigned`	`smc_4core_cpu_pkg::NumCpuInterrupts`	Number of interrupt lines into the cluster, from smc_4core_cpu_pkg.
`NumSramBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumSramBanks`	Number of scratch RAM banks; sizes the scratch RAM port arrays.
`NumIcacheTagBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumIcacheTagBanks`	Number of instruction-cache tag banks; sizes the instruction-cache tag port arrays.
`NumIcacheDataBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumIcacheDataBanks`	Number of instruction-cache data banks; sizes the instruction-cache data port arrays.
`NumDcacheTagBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumDcacheTagBanks`	Number of data-cache tag banks; sizes the data-cache tag port arrays.
`NumDcacheDataBanks`	`int unsigned`	`chipyard_4core_mem_pkg::NumDcacheDataBanks`	Number of data-cache data banks; sizes the data-cache data port arrays.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	SMC core clock for the cluster, the front-port demux, cpu_ctrl and the boot ROM interface.
`clk_ref_i`	input	`logic`	Reference clock for the cpu_ctrl reference counter.
`rst_isolate_ni`	input	`logic`	Active-low reset for the cluster-boundary AXI isolate modules.
`rst_primary_smc_clk_ni`	input	`logic`	Active-low primary reset in the SMC clock domain for the front-port demux, AXI-Lite converter and cpu_ctrl.
`rst_warm_smc_clk_ni`	input	`logic`	Active-low warm reset in the SMC clock domain; holds the cluster core and uncore resets asserted and selects the default core reset vector.
`fuse_reset_ni`	input	`logic`	Active-low reset for the scratch RAM zero-fill sequencer; its release starts the zero-fill.
`scan_rst_ni`	input	`logic`	Active-low scan reset, passed to cpu_ctrl, which does not use it.
`chiplet_is_primary_i`	input	`logic`	High on the primary chiplet; reported by cpu_ctrl in SMC_ATTRIBUTES.
`axi_front_port_req_i`	input	`smc_pkg::smc_local_32_64_8_12_axi_req_t`	Front-port AXI request from the local fabric; addresses in the SMC_CPU_CTRL window go to cpu_ctrl, all others to the cluster L2 frontend.
`axi_front_port_resp_o`	output	`smc_pkg::smc_local_32_64_8_12_axi_resp_t`	Front-port AXI response to the local fabric.
`axi_mmio_port_req_o`	output	`smc_pkg::smc_cpu_mmio_axi_req_t`	Cluster MMIO AXI master request to the smc_fabric input fabric.
`axi_mmio_port_resp_i`	input	`smc_pkg::smc_cpu_mmio_axi_resp_t`	Cluster MMIO AXI master response from the smc_fabric input fabric.
`interrupts_i`	input	`logic [NumCpuInterrupts-1:0]`	Interrupt vector from smc_base, passed unchanged to the cluster.
`wb_reg_pc_o`	output	`logic [NumCpuCores-1:0][57:0]`	Per-core writeback program counter from the cluster, zero while the cluster boundary is isolated.
`wdt_timeout_cluster_o`	output	`logic [NumCpuCores-1:0]`	Per-core first-stage watchdog timeout from the cluster, low while the cluster boundary is isolated.
`wdt_second_timeout_o`	output	`logic`	Second-stage watchdog timeout from cpu_ctrl, registered on clk_i.
`cluster_ded_o`	output	`logic`	Registered OR of the cluster's uncorrectable-error flags, cleared while the cluster uncore reset is asserted.
`rom_intf_req_o`	output	`rom_req_t`	Boot ROM read request from the TileLink-to-ROM bridge, clocked by clk_i, with the write fields tied to zero.
`rom_intf_rsp_i`	input	`rom_rsp_t`	Boot ROM read data for the TileLink-to-ROM bridge.
`scratch_ram_intf_req_o`	output	`scratch_ram_req_t`	Scratch RAM bank requests, driven by the zero-fill sequencer until the zero-fill completes.
`scratch_ram_intf_rsp_i`	input	`scratch_ram_rsp_t`	Scratch RAM bank read data.
`l1_icache_tag_intf_req_o`	output	`l1_icache_tag_req_t`	Instruction-cache tag bank requests.
`l1_icache_tag_intf_rsp_i`	input	`l1_icache_tag_rsp_t`	Instruction-cache tag bank read data.
`l1_icache_data_intf_req_o`	output	`l1_icache_data_req_t`	Instruction-cache data bank requests.
`l1_icache_data_intf_rsp_i`	input	`l1_icache_data_rsp_t`	Instruction-cache data bank read data.
`l1_dcache_tag_intf_req_o`	output	`l1_dcache_tag_req_t`	Data-cache tag bank requests.
`l1_dcache_tag_intf_rsp_i`	input	`l1_dcache_tag_rsp_t`	Data-cache tag bank read data.
`l1_dcache_data_intf_req_o`	output	`l1_dcache_data_req_t`	Data-cache data bank requests.
`l1_dcache_data_intf_rsp_i`	input	`l1_dcache_data_rsp_t`	Data-cache data bank read data.
`disable_sram_auto_init_i`	input	`logic`	High skips the scratch RAM zero-fill after fuse_reset_ni releases.
`init_mem_done_o`	output	`logic`	High once the scratch RAM zero-fill has completed or been skipped.
`rom_flip_endianness_i`	input	`logic`	High byte-reverses each ROM word returned to the cluster.
`test_en_i`	input	`logic`	Scan test mode enable for the front-port demux, AXI-Lite converter and cluster debug clock gate.
`smc_cpu_jtag_TCK_i`	input	`logic`	JTAG test clock for the cluster debug transport module.
`smc_cpu_jtag_TMS_i`	input	`logic`	JTAG test mode select for the cluster debug transport module.
`smc_cpu_jtag_TDI_i`	input	`logic`	JTAG test data into the cluster debug transport module.
`smc_cpu_jtag_TDO_data_o`	output	`logic`	JTAG test data out of the cluster debug transport module.
`smc_cpu_jtag_reset_i`	input	`logic`	Active-high asynchronous reset of the cluster JTAG debug transport module (TAP) and of the debug module's DMI interface.
`smc_cpu_jtag_mfr_id_i`	input	`logic [10:0]`	Manufacturer ID reported in the cluster JTAG IDCODE.
`smc_cpu_jtag_part_number_i`	input	`logic [15:0]`	Part number reported in the cluster JTAG IDCODE.
`smc_cpu_jtag_version_i`	input	`logic [3:0]`	Version reported in the cluster JTAG IDCODE.