smc_data_accelerator_wrap

Wrap the SMC DMA and zeroer with address-based demux and mux.

Adapts accelerator control and master data ports to the SMC fabric. Exposes status and clock-gater activity indicators alongside clock-gating control. The control demux decodes the DMA and zeroer windows from smc_top_addrmap_pkg and sends any other address to the DMA; the master mux prepends a source bit to the transfer IDs.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`DMA_BUFFER_DEPTH`	`int unsigned`	`16`	DMA buffer depth in beats.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	SMC core clock.
`rst_ni`	input	`logic`	Primary reset, active-low, synchronized to the SMC core clock.
`test_en_i`	input	`logic`	Scan test mode enable, active-high; forwarded to the DMA, the zeroer, and the AXI demux and mux.
`dma_cg_en_i`	input	`logic`	Enables idle clock gating of the DMA front end when high; while low its clock runs continuously.
`zeroer_cg_en_i`	input	`logic`	Enables idle clock gating of the zeroer datapath when high; while low its clock runs continuously.
`cg_hysteresis_i`	input	`logic [smc_pkg::CgHysteresisW-1:0]`	Idle SMC core clock cycles the DMA and zeroer clock gates wait after going idle before stopping their clocks.
`ctrl_axi_req_i`	input	`smc_pkg::smc_local_32_64_8_12_axi_req_t`	Control request from the local crossbar for the DMA and zeroer register windows.
`ctrl_axi_resp_o`	output	`smc_pkg::smc_local_32_64_8_12_axi_resp_t`	Control response to the local crossbar.
`mst_axi_req_o`	output	`smc_pkg::smc_input_fabric_56_64_4_12_axi_req_t`	Transfer request from the DMA or zeroer into the input fabric.
`mst_axi_resp_i`	input	`smc_pkg::smc_input_fabric_56_64_4_12_axi_resp_t`	Transfer response from the input fabric.
`dma_busy_o`	output	`logic`	High while the DMA front end or back end has a transfer in flight.
`dma_intp_o`	output	`logic`	DMA completion interrupt, a one-cycle pulse when dma_busy_o falls.
`zeroer_busy_o`	output	`logic`	High while the zeroer has work in flight.
`zeroer_intp_o`	output	`logic`	Zeroer completion interrupt, a one-cycle pulse when zeroer_busy_o falls while its interrupt is enabled; held low when the zeroer enters its error state.
`dma_frontend_clk_active_o`	output	`logic`	High while the DMA front-end gated clock is running.
`dma_frontend_bus_active_o`	output	`logic`	High while the DMA control port has an AXI transaction outstanding.
`zeroer_clk_active_o`	output	`logic`	High while the zeroer datapath gated clock is running.
`zeroer_bus_active_o`	output	`logic`	High while the zeroer control bus has traffic.