smc_dfd_wrap

Wrap the SMC design-for-debug logic: one CLA and one DST behind an APB register port.

Reduces the 64-lane debug bus to 16 lanes through eight level-3 and four level-2 debug-bus muxes, and runs the muxes and the DFD IP on a locally gated copy of clk_smc_i. Generates the CLA time tick from clk_ref_i edges, masks the CLA cross-trigger and halt-clock outputs, and leaves the trace sink RAMs outside the block.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`BASE_ADDR`	`logic [22:0]`	`0`	Base address of the CLA and DST registers, passed to the DFD IP as its MMR base address.
`NUM_INPUT_LANES`	`int unsigned`	`64`	Number of lanes on debug_bus_i. The eight level-3 muxes always read 64 lanes: a smaller value makes their part-selects run past the top of debug_bus_i, and lanes above 64 are ignored.
`REF_CNT_W`	`int unsigned`	`8`	Width of the reference tick accounting counters. Bounds how far clk_gated_i may fall behind clk_ref_i before ticks are lost; 2**REF_CNT_W ref cycles of slack.
`LaneWidth`	`int unsigned`	`16`	Width of one debug-bus lane in the mux tree and the DFD IP.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_smc_i`	input	`logic`	SMC core clock, gated locally to clock the debug-bus muxes, the DFD IP and the time-tick counter.
`clk_ref_i`	input	`logic`	Reference clock; each rising edge produces one CLA time tick in the gated SMC clock domain.
`rst_primary_ni`	input	`logic`	Active-low primary reset for the DFD logic, also synchronized into clk_ref_i for the reference counter.
`apb_smc_dfd_reg_req_i`	input	`smc_pkg::smc_dfd_apb_req_t`	APB request to the CLA and DST registers.
`apb_smc_dfd_reg_resp_o`	output	`smc_pkg::smc_dfd_apb_resp_t`	APB response from the CLA and DST registers.
`dfd_enables_i`	input	`smc_pkg::dfd_enable_t`	DFD control fields: dfd_cg_en set stops the local clock unless dfd_force_clk_en is set; bit 0 of xtrig_clk_halt_mask passes the CLA cross-trigger and halt-clock outputs. The clock runs while rst_primary_ni is low.
`external_action_debug_interrupt_o`	output	`logic`	Debug interrupt raised by a CLA external action.
`external_action_custom_o`	output	`logic [cla_pkg::CLA_NUMBER_OF_CUSTOM_ACTIONS-1:0]`	Custom CLA external-action outputs, one bit per custom action.
`xtrigger_ss_o`	output	`smc_pkg::xtrigger_t`	Cross-trigger lanes from the CLA, forced low unless bit 0 of the clock-halt trigger mask is set.
`xtrigger_ss_i`	input	`smc_pkg::xtrigger_t`	Cross-trigger lanes into the CLA.
`tdr_dbg_ctrl_clock_stop_en_i`	input	`logic`	Enables reporting a CLA halt-clock action as a clock stop.
`tdr_dbg_ctrl_clocks_stopped_by_cla_o`	output	`logic`	High while a CLA halt-clock action, enabled by the mask and tdr_dbg_ctrl_clock_stop_en_i, is requesting a clock stop.
`dbg_mux_sel_csr_i`	input	`tt_dbm_pkg::DbgMuxSelMmr_s`	Debug-bus mux select register, shared by every level-2 and level-3 mux.
`debug_bus_i`	input	`logic [NUM_INPUT_LANES*LaneWidth-1:0]`	Debug-bus lanes from the SMC into the level-3 mux stage.
`debug_marker_o`	output	`logic [7:0]`	Debug marker from the CLA.
`trace_mem_req_o`	output	`trace_mem_pkg::SinkMemPktIn_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Requests from the DST trace sink to the trace RAMs outside this block, one per RAM instance.
`trace_mem_resp_i`	input	`trace_mem_pkg::SinkMemPktOut_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Read data from the external trace RAMs to the DST trace sink.
`test_en_i`	input	`logic`	Active-high DFT test-mode enable: forces the DFD clock gates on and selects scan_rst_ni as the DFD IP and reference-counter reset.
`scan_rst_ni`	input	`logic`	Active-low scan reset used by the DFD IP and the reference-clock reset synchronizer in test mode.