smc_dfx_ctrl_status_wrap

Expose SMC DFX control and status CSRs.

Bridges software-visible DFX controls onto the internal AXI-Lite map. Reports memory-repair and MBIST status in STATUS_SMU and drives the DEBUG_CTRL and DEBUG_BUS_MUX fields that configure smc_dfd_wrap; debug-bus mux segments 8 to 15 and the fine-grain time field have no register and are tied to zero.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	SMC core clock.
`rst_ni`	input	`logic`	Primary reset, active-low, synchronized to the SMC core clock; returns the DFX control and status registers to their reset values.
`axil_dfx_csr_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the DFX control window.
`axil_dfx_csr_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response to the internal CSR crossbar.
`mem_repair_done_i`	input	`logic`	Memory repair has finished; reported in STATUS_SMU.
`mem_repair_success_i`	input	`logic`	Memory repair succeeded; reported in STATUS_SMU.
`mem_repair_abort_i`	input	`logic`	Memory repair was aborted; reported in STATUS_SMU.
`mbist_done_i`	input	`logic`	Memory BIST has finished; reported in STATUS_SMU.
`mbist_pass_i`	input	`logic`	Memory BIST passed; reported in STATUS_SMU.
`mbist_abort_i`	input	`logic`	Memory BIST was aborted; reported in STATUS_SMU.
`dfd_enables_o`	output	`smc_pkg::dfd_enable_t`	DEBUG_CTRL clock-gate, force-clock, GPIO, DTB, cross-trigger halt mask and debug marker fields.
`dbg_mux_sel_csr_o`	output	`tt_dbm_pkg::DbgMuxSelMmr_s`	Debug-bus mux mode, ID and segment selects from DEBUG_BUS_MUX.