smc_efuse_wrapper

Wrap the vendor eFuse controller for the SMC peripheral map.

Presents the eFuse CSR window on the peripheral AXI-Lite map. Bridges fuse sense, program, shadow-register, and DFT sidebands into the SMC peripheral domain. JTAG AXI-Lite accesses receive an error response with data 0xBADCAB1E when the SEP lifecycle state is PROD or RMA_SiP or fails its integrity check, except reads of JTAG_PUBLIC_IDENTITY outside an integrity error.

Ports

Table 1. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	SMC core clock for the eFuse controller and JTAG access filter.
`rst_ni`	input	`logic`	Primary reset, active-low, synchronized to clk_i.
`test_en_i`	input	`logic`	DFT test-mode enable, active-high.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low, used while test_en_i is high.
`axil_req_i`	input	`smc_pkg::smc_axil_32_32_req_t`	Functional AXI4-Lite slave (from SMC peripherals xbar) request.
`axil_resp_o`	output	`smc_pkg::smc_axil_32_32_resp_t`	Functional AXI4-Lite slave (from SMC peripherals xbar) response.
`axil_smc_otp_jtag_req_i`	input	`smc_pkg::smc_axil_32_32_req_t`	JTAG AXI4-Lite slave request.
`axil_smc_otp_jtag_resp_o`	output	`smc_pkg::smc_axil_32_32_resp_t`	JTAG AXI4-Lite slave response.
`lc_state_i`	input	`logic [2*smc_pkg::LcStateWidth-1:0]`	LC state from SEP (differentially encoded); PROD and RMA_SiP restrict JTAG access.
`lc_sigint_err_o`	output	`logic`	Integrity error from the differential decode of lc_state_i, active-high; also blocks JTAG access.
`fuse_bank_ctrl_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	eFuse SHIM CSR AXI4-Lite request.
`fuse_bank_ctrl_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	eFuse SHIM CSR AXI4-Lite response.
`efuse_shim_command_req_o`	output	`smc_efuse_pkg::fuse_command_req_t`	Fuse sense and program command request to the SHIM state machine.
`efuse_shim_command_resp_i`	input	`smc_efuse_pkg::fuse_command_resp_t`	Fuse command response from the SHIM state machine.
`sep_security_disable_i`	input	`logic`	Security disable from the SEP eFuse controller, active-high; skips automatic fuse sensing and releases the shadow registers without it.
`ext_boot_seq_done_i`	input	`logic`	External boot sequence done (gate the released reset).
`reset_n_o`	output	`logic`	Active-low reset released through a synchronizer once fuse sensing and ext_boot_seq_done_i are both done.
`fuse_sense_done_o`	output	`logic`	High once shadow-register loading from the fuses completes.
`shadow_regs_o`	output	`smc_efuse_pkg::efuse_map_t`	Shadow-register contents; zero until fuse sensing completes unless sep_security_disable_i is set.
`efuse_debug_o`	output	`logic [9:0]`	eFuse controller status, from bit 0: shadow-register write and read locks, program and read locks, write-setup-only, LC-state access, read and program timeouts, request error and secure-test-mode block.
`locked_field_access_interrupt_o`	output	`logic`	High during an access to the eFuse map window that a field lock blocks.