smc_internal_regs

Aggregate SMC internal CSR blocks on the internal AXI-Lite and APB maps.

Decodes filter, remap, mailbox, DFT, and base-config CSRs and exposes their structs. Publishes the SMC address window, clock-gate enables, and AXI hang-detector config from smc_base_config for consumers outside this module. Carries DFD, TDR debug, and trace-sink memory sidebands plus DFT status and clock-gater activity indicators. The mailbox, filter and remap register blocks each run on their own idle-gated copy of the SMC core clock. Writes to a filter whose FILTER_CONFIG.locked bit is set receive DECERR; reads of a locked filter still complete.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`NUM_OUTBOUND_FILTERS`	`int unsigned`	`16`	Number of outbound filter register blocks; sizes the outbound filter CSR arrays and the AXI-Lite demux that selects one block per 32-byte address window.
`NUM_INBOUND_FILTERS`	`int unsigned`	`16`	Number of inbound filter register blocks; sizes the inbound filter CSR arrays and the AXI-Lite demux that selects one block per 32-byte address window.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_ref_i`	input	`logic`	Reference clock, used only by the DFD block for the CLA time tick.
`clk_smc_i`	input	`logic`	SMC core clock for every CSR block, and the source of their gated clocks.
`rst_primary_smc_clk_ni`	input	`logic`	Primary reset, active-low, synchronized to the SMC core clock; resets every CSR block in this module.
`outbound_filter_status_i`	input	`filter_ctrl_reg_pkg::filter_ctrl__in_t`	Hardware status of each outbound filter entry, from the output fabric.
`outbound_filter_ctrl_o`	output	`filter_ctrl_reg_pkg::filter_ctrl__out_t`	Register configuration of each outbound filter entry.
`inbound_filter_status_i`	input	`filter_ctrl_reg_pkg::filter_ctrl__in_t`	Hardware status of each inbound filter entry, from the input fabric.
`inbound_filter_ctrl_o`	output	`filter_ctrl_reg_pkg::filter_ctrl__out_t`	Register configuration of each inbound filter entry.
`mR_ctrl_o`	output	`output_remap_reg_pkg::output_remap__out_t`	Register configuration of each M-mode output remap region.
`xR_ctrl_o`	output	`output_remap_reg_pkg::output_remap__out_t`	Register configuration of each Xvisor output remap region.
`aR_ctrl_o`	output	`alias_remap_reg_pkg::alias_remap__out_t`	Register configuration of each alias remap region.
`apb_smc_dfd_reg_req_i`	input	`smc_pkg::smc_dfd_apb_req_t`	APB request from the local crossbar for the CLA and DST registers.
`apb_smc_dfd_reg_resp_o`	output	`smc_pkg::smc_dfd_apb_resp_t`	APB response to the local crossbar.
`axil_inbound_filter_ctrl_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the inbound filter windows.
`axil_inbound_filter_ctrl_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the inbound filter windows.
`axil_outbound_filter_ctrl_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the outbound filter windows.
`axil_outbound_filter_ctrl_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the outbound filter windows.
`axil_mR_ctrl_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the M-mode remap windows.
`axil_mR_ctrl_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the M-mode remap windows.
`axil_xR_ctrl_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the Xvisor remap windows.
`axil_xR_ctrl_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the Xvisor remap windows.
`axil_aR_ctrl_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the alias remap windows.
`axil_aR_ctrl_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the alias remap windows.
`axil_mailbox_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the mailbox window.
`axil_mailbox_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the mailbox window.
`axil_dfx_csr_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the DFX control window.
`axil_dfx_csr_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the DFX control window.
`inbound_interrupt_o`	output	`logic [smc_pkg::NumMailboxes-1:0]`	Per-mailbox inbound data interrupt; smc_base routes it to the SMC CPU.
`outbound_interrupt_o`	output	`logic [smc_pkg::NumMailboxes-1:0]`	Per-mailbox outbound data interrupt; smc_base drives it out of the SMC.
`axil_smc_base_config_req_i`	input	`smc_pkg::smc_axil_32_64_req_t`	Request from the internal CSR crossbar for the base-config window.
`axil_smc_base_config_resp_o`	output	`smc_pkg::smc_axil_32_64_resp_t`	Response for the base-config window.
`smc_global_base_o`	output	`smc_pkg::smc_axi_addr_t`	SMC global base address from GLOBAL_BASE.
`smc_local_base_o`	output	`smc_pkg::smc_axi_addr_t`	SMC local base address from LOCAL_BASE.
`smc_region_size_o`	output	`logic [31:0]`	SMC region size in bytes from REGION_SIZE.
`cg_ctrl_dma_cg_en_o`	output	`logic`	Enables idle clock gating of the DMA when high.
`cg_ctrl_ob_filter_axi_cg_en_o`	output	`logic`	Enables idle clock gating of the outbound filter datapath when high.
`cg_ctrl_ib_filter_axi_cg_en_o`	output	`logic`	Enables idle clock gating of the inbound filter datapath when high.
`cg_ctrl_output_fabric_cg_en_o`	output	`logic`	Enables idle clock gating of the output fabric when high.
`cg_ctrl_zeroer_cg_en_o`	output	`logic`	Enables idle clock gating of the zeroer when high.
`cg_ctrl_i3c_cg_en_o`	output	`logic`	In smc, stops the I3C peripheral clock when high.
`cg_ctrl_avs_cg_en_o`	output	`logic`	In smc, stops the AVSBus controller peripheral and reference clocks when high.
`cg_ctrl_i2c_cg_en_o`	output	`logic`	In smc, stops the I2C peripheral clock when high.
`cg_ctrl_uart_cg_en_o`	output	`logic`	In smc, stops the UART peripheral clock when high.
`cg_ctrl_tel_cg_en_o`	output	`logic`	In smc, stops the telemetry unit's gated SMC and telemetry clocks when high.
`cg_ctrl_hysteresis_o`	output	`smc_pkg::cg_hyster_t`	Idle SMC core clock cycles every idle clock gate waits before stopping its clock; also used by the gates in this module.
`hang_det_sys_axi_enable_o`	output	`logic`	Enables the system AXI hang detector.
`hang_det_sys_axi_irq_en_o`	output	`logic`	Enables the system AXI hang interrupt.
`hang_det_sys_axi_irq_test_o`	output	`logic`	Forces the system AXI hang interrupt high.
`hang_det_sys_axi_threshold_o`	output	`logic [19:0]`	Stall cycles after which the system AXI hang detector fires.
`hang_det_sep_axi_enable_o`	output	`logic`	Enables the SEP AXI hang detector.
`hang_det_sep_axi_irq_en_o`	output	`logic`	Enables the SEP AXI hang interrupt.
`hang_det_sep_axi_irq_test_o`	output	`logic`	Forces the SEP AXI hang interrupt high.
`hang_det_sep_axi_threshold_o`	output	`logic [19:0]`	Stall cycles after which the SEP AXI hang detector fires.
`hang_det_data_accel_enable_o`	output	`logic`	Enables the data-accelerator AXI hang detector.
`hang_det_data_accel_irq_en_o`	output	`logic`	Enables the data-accelerator AXI hang interrupt.
`hang_det_data_accel_irq_test_o`	output	`logic`	Forces the data-accelerator AXI hang interrupt high.
`hang_det_data_accel_threshold_o`	output	`logic [19:0]`	Stall cycles after which the data-accelerator AXI hang detector fires.
`hang_det_sys_axi_irq_i`	input	`logic`	System AXI hang detector interrupt, for HANG_DET_SYS_AXI_CTRL.irq.
`hang_det_sep_axi_irq_i`	input	`logic`	SEP AXI hang detector interrupt, for HANG_DET_SEP_AXI_CTRL.irq.
`hang_det_data_accel_irq_i`	input	`logic`	Data-accelerator AXI hang detector interrupt, for HANG_DET_DATA_ACCEL_CTRL.irq.
`cla_interrupt_o`	output	`logic`	Debug interrupt raised by a CLA external action.
`cla_ext_action_custom_o`	output	`logic [cla_pkg::CLA_NUMBER_OF_CUSTOM_ACTIONS-1:0]`	Custom CLA external-action outputs, one bit per action.
`xtrigger_ss_o`	output	`smc_pkg::xtrigger_t`	Cross-trigger outputs from the CLA to the subsystem cross-trigger network, masked by the DFD cross-trigger clock-halt mask.
`xtrigger_ss_i`	input	`smc_pkg::xtrigger_t`	Cross-trigger inputs from the subsystem cross-trigger network to the CLA.
`tdr_dbg_ctrl_clock_stop_en_i`	input	`logic`	Enables reporting a CLA halt-clock action as a clock stop.
`tdr_dbg_ctrl_clocks_stopped_by_cla_o`	output	`logic`	High while an enabled CLA halt-clock action requests a clock stop.
`debug_bus_i`	input	`logic [1023:0]`	Debug bus observed by the CLA, 64 lanes of 16 bits whose upper 32 lanes carry adopter signals; not synchronized to the SMC core clock.
`debug_marker_o`	output	`logic [7:0]`	Debug marker byte driven by the CLA.
`trace_mem_req_o`	output	`trace_mem_pkg::SinkMemPktIn_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Requests from the DFD trace sink to the external trace RAMs.
`trace_mem_resp_i`	input	`trace_mem_pkg::SinkMemPktOut_s [tn_pkg::TRC_RAM_INSTANCES-1:0]`	Read data from the external trace RAMs.
`test_en_i`	input	`logic`	Scan test mode enable, active-high; forces the CSR clock gates on and switches the DFD block onto scan_rst_ni.
`scan_rst_ni`	input	`logic`	Scan reset, active-low, used by the DFD block while test_en_i is high.
`mem_repair_done_i`	input	`logic`	Memory repair has finished; reported in the DFX STATUS_SMU register.
`mem_repair_success_i`	input	`logic`	Memory repair succeeded; reported in the DFX STATUS_SMU register.
`mem_repair_abort_i`	input	`logic`	Memory repair was aborted; reported in the DFX STATUS_SMU register.
`mbist_done_i`	input	`logic`	Memory BIST has finished; reported in the DFX STATUS_SMU register.
`mbist_pass_i`	input	`logic`	Memory BIST passed; reported in the DFX STATUS_SMU register.
`mbist_abort_i`	input	`logic`	Memory BIST was aborted; reported in the DFX STATUS_SMU register.
`mailbox_clk_active_o`	output	`logic`	High while the mailbox gated clock is running.
`mailbox_bus_active_o`	output	`logic`	High while the mailbox register port has a transaction outstanding.
`ob_filter_clk_active_o`	output	`logic`	High while the outbound filter register gated clock is running.
`ob_filter_bus_active_o`	output	`logic`	High while the outbound filter register port has a transaction outstanding.
`ib_filter_clk_active_o`	output	`logic`	High while the inbound filter register gated clock is running.
`ib_filter_bus_active_o`	output	`logic`	High while the inbound filter register port has a transaction outstanding.
`mmode_remap_clk_active_o`	output	`logic`	High while the M-mode remap register gated clock is running.
`mmode_remap_bus_active_o`	output	`logic`	High while the M-mode remap register port has a transaction outstanding.
`xvisor_remap_clk_active_o`	output	`logic`	High while the Xvisor remap register gated clock is running.
`xvisor_remap_bus_active_o`	output	`logic`	High while the Xvisor remap register port has a transaction outstanding.
`alias_remap_clk_active_o`	output	`logic`	High while the alias remap register gated clock is running.
`alias_remap_bus_active_o`	output	`logic`	High while the alias remap register port has a transaction outstanding.