smc_misc_wrap

Wrap SMC miscellaneous register targets on the misc AXI-Lite map.

Demultiplexes the misc map onto cold scratch registers, cold-and-warm scratch registers, the chip_config registers (version ID, chip ID and lifecycle state) and the NDM reset registers. Addresses outside those windows reach an error slave that returns DECERR with read data 0xBADCAB1E.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`CHIP_ID`	`int unsigned`	`0`	Chip identifier reported by the chip_config CHIP_ID register.
`LC_STATE_WIDTH`	`int unsigned`	`8`	Width of lc_state_i, which the chip_config LC_STATE register reports.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_i`	input	`logic`	SMC core clock.
`rst_ni`	input	`logic`	Primary reset, active-low, synchronized to the SMC core clock; resets the demux, the cold scratch registers, chip_config, and the NDM reset registers.
`rst_warm_ni`	input	`logic`	Warm reset, active-low, synchronized to the SMC core clock; resets the cold-and-warm scratch registers.
`test_en_i`	input	`logic`	Scan test mode enable, forwarded to the test input of the AXI-Lite demux.
`reg_axi_lite_req_i`	input	`smc_pkg::smc_axil_32_32_req_t`	Request from the peripheral crossbar for the misc map.
`reg_axi_lite_resp_o`	output	`smc_pkg::smc_axil_32_32_resp_t`	Response to the peripheral crossbar.
`lc_state_i`	input	`logic [LC_STATE_WIDTH-1:0]`	Lifecycle state, reported through the chip_config LC_STATE register.
`ndmreset_request_i`	input	`logic [smc_config_pkg::CpuClusterCount-1:0]`	NDM reset request per CPU cluster, synchronized to the SMC core clock and readable in the NDMRESET_REQUEST register.
`ndmreset_process_o`	output	`logic [smc_config_pkg::CpuClusterCount-1:0]`	Firmware response to each cluster's NDM reset request, from the NDMRESET_PROCESS register.