smc_peripherals

Aggregate SMC peripherals, eFuse, and pad-facing I/O.

Instantiates the peripheral CSR crossbar and its clock-domain crossings, the padring and GPIOs, UART, I2C, I3C, telemetry receivers, AVSBus controller, eFuse wrapper, system timer, misc registers and the SMC reset unit. The SPI controller is outside this module: its signals only pass through the padring to the SPI pads. Returns UART/GPIO interrupts, the gated I3C clock, and debug buses.

EFUSE_SHIM_SIZE is the vendor eFuse shim CSR carve-out at the base of the opaque smc_external window. Each peripheral clock-gate enable stops its clock when high and steers that peripheral's crossbar leg into an error slave, so an access to a gated peripheral completes with SLVERR and read data 0xBADCAB1E instead of stalling. The DTP CSR, smc_external, eFuse shim and JTAG eFuse AXI-Lite ports each pass through an axi_cut.

Parameters

Table 1. Parameters
Name	Type	Default	Description
`MAX_TRANS`	`int unsigned`	`2`	Maximum outstanding transactions of the padring GPIO demux and of each GPIO interface.
`EFUSE_SHIM_SIZE`	`int unsigned`	`'h4`	Vendor eFuse shim CSR block carved off the base of the smc_external window; literal because the open smc_external map is opaque. Passed to the peripheral crossbar.

Ports

Table 2. Ports
Name	Direction	Type	Description
`clk_ref_i`	input	`logic`	Reference clock for the reset unit, the AVSBus controller and the peripheral CDC.
`clk_smc_i`	input	`logic`	SMC core clock for the peripheral crossbar and the SMC-clock peripherals.
`clk_periph_i`	input	`logic`	Peripheral clock for the UART, I2C, I3C and AVSBus register interfaces.
`test_en_i`	input	`logic`	DFT test-mode enable, active-high; bypasses the peripheral clock gates and selects the scan reset.
`scan_rst_ni`	input	`logic`	DFT scan reset, active-low, used in place of functional resets while test_en_i is high.
`clk_telemetry_i`	input	`logic`	Telemetry clock, gated by tel_cg_en_i before it reaches the telemetry receivers.
`rst_telemetry_ni`	input	`logic`	Telemetry-domain reset, active-low, for the telemetry receivers' ATB FIFOs.
`i3c_cg_en_i`	input	`logic`	Stops the I3C peripheral clock when high; synchronized to the peripheral clock. I3C accesses answer SLVERR while high.
`avs_cg_en_i`	input	`logic`	Stops the AVSBus controller peripheral and reference clocks when high. AVSBus accesses answer SLVERR while high.
`i2c_cg_en_i`	input	`logic`	Stops the I2C peripheral clock when high. I2C accesses answer SLVERR while high.
`uart_cg_en_i`	input	`logic`	Stops the UART peripheral clock when high. UART accesses answer SLVERR while high.
`tel_cg_en_i`	input	`logic`	Stops the telemetry receivers' gated SMC and telemetry clocks when high. Telemetry accesses answer SLVERR while high.
`axil_peripherals_req_i`	input	`smc_pkg::smc_axil_32_32_req_t`	Request from the local crossbar into the peripheral crossbar.
`axil_peripherals_resp_o`	output	`smc_pkg::smc_axil_32_32_resp_t`	Response to the local crossbar.
`axil_log_engine_req_o`	output	`smc_pkg::smc_axil_56_64_req_t`	Log-engine fetch request from the UART, moved onto the SMC clock.
`axil_log_engine_resp_i`	input	`smc_pkg::smc_axil_56_64_resp_t`	Log-engine fetch response on the SMC clock.
`axil_dtp_csr_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	DTP CSR request with its address rebased to zero at the DTP control window.
`axil_dtp_csr_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	DTP CSR response.
`smc_external_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	Request for the part of the smc_external window above the eFuse shim carve-out.
`smc_external_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	Response from the smc_external window.
`axil_smc_otp_jtag_req_i`	input	`smc_pkg::smc_axil_32_32_req_t`	JTAG request into the eFuse wrapper, filtered by lifecycle state.
`axil_smc_otp_jtag_resp_o`	output	`smc_pkg::smc_axil_32_32_resp_t`	Response to the JTAG eFuse access path.
`lsio_interface_select_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	LSIO select per pad from the padring, high where a peripheral function claims the pad.
`pad2core_i`	input	`logic [smc_pkg::NumGpioWraps-1:0]`	Value received from each GPIO pad.
`core2pad_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Value driven onto each GPIO pad.
`pad2core_en_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Input enable of each GPIO pad.
`core2pad_en_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Output enable of each GPIO pad.
`spi_enable_i`	input	`logic`	Hands the SPI pads to the external SPI host, active-high.
`spi_clk_i`	input	`logic`	Serial clock from the external SPI host, driven onto the SPI clock pad.
`spi_txd_i`	input	`logic [7:0]`	Transmit data from the external SPI host, one bit per data pad.
`spi_cs_n_i`	input	`logic`	Chip select from the external SPI host, active-low.
`spi_cs_oe_n_i`	input	`logic`	Output enable for the chip-select pad, active-low.
`spi_cs_ie_n_i`	input	`logic`	Input enable for the chip-select pad, active-low.
`spi_clk_ie_n_i`	input	`logic`	Input enable for the SPI clock pad, active-low.
`spi_clk_oe_n_i`	input	`logic`	Output enable for the SPI clock pad, active-low.
`spi_dqs_ie_n_i`	input	`logic`	Input enable for the data-strobe pad, active-low.
`spi_dqs_oe_n_i`	input	`logic`	Output enable for the data-strobe pad, active-low; the pad drives zero when enabled.
`spi_dq_ie_n_i`	input	`logic [7:0]`	Input enables for the data pads, active-low, one bit per data pad.
`spi_dq_oe_n_i`	input	`logic [7:0]`	Output enables for the data pads, active-low, one bit per data pad.
`spi_rxd_o`	output	`logic [7:0]`	Receive data sampled from the data pads, to the external SPI host.
`spi_rxds_o`	output	`logic`	Read data strobe sampled from the data-strobe pad, used in DDR mode.
`spi_mem_rebar_oepad_i`	input	`logic`	Output enable for the SPI DQS loopback pad, active-high.
`spi_mem_rebar_opad_i`	input	`logic`	Data driven onto the SPI DQS loopback pad.
`spi_mem_rebar_iepad_i`	input	`logic`	Input enable for the SPI DQS loopback pad, active-high.
`spi_mem_rebar_ipad_o`	output	`logic`	Value sampled from the SPI DQS loopback pad.
`telemetry_atdata_i`	input	`telemetry_receiver_pkg::telemetry_data_t [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB trace data per telemetry receiver.
`telemetry_atid_i`	input	`telemetry_receiver_pkg::atb_id_t [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB trace source ID per receiver.
`telemetry_atready_o`	output	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB ready from each receiver.
`telemetry_atvalid_i`	input	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB data valid per receiver.
`telemetry_afvalid_o`	output	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB flush request from each receiver.
`telemetry_afready_i`	input	`logic [smc_config_pkg::NumTelemetryReceivers-1:0]`	ATB flush acknowledge per receiver.
`lc_state_i`	input	`logic [2*smc_pkg::LcStateWidth-1:0]`	Differentially encoded lifecycle state, used by the eFuse JTAG access filter and reported in chip_config.
`lc_sigint_err_o`	output	`logic`	Integrity error from the differential decode of lc_state_i, active-high.
`chiplet_is_primary_i`	input	`logic`	Makes the system timer drive the timer sync pads when high and follow them when low.
`timer_count_o`	output	`logic [63:0]`	Live 64-bit system timer count.
`system_timer_octs_credits_debug_o`	output	`logic [8:0]`	Current system timer credit count.
`system_timer_octs_credits_left_debug_o`	output	`logic`	High while system timer credits remain.
`fuse_bank_ctrl_req_o`	output	`smc_pkg::smc_axil_32_32_req_t`	Request to the vendor eFuse shim CSRs.
`fuse_bank_ctrl_resp_i`	input	`smc_pkg::smc_axil_32_32_resp_t`	Response from the vendor eFuse shim CSRs.
`boot_stall_jtag_ovrd_i`	input	`logic`	Replaces the boot-stall pad value with boot_stall_jtag_val_i when high.
`boot_stall_jtag_val_i`	input	`logic`	Boot-stall value used while the JTAG override is set.
`boot_stall_processed_o`	output	`logic`	Boot stall synchronized to the SMC clock and made sticky: once low it stays low until the next primary reset; while high it holds fuse_reset_n_o low.
`efuse_shim_command_req_o`	output	`smc_efuse_pkg::fuse_command_req_t`	Fuse sense and program command request to the shim state machine.
`efuse_shim_command_resp_i`	input	`smc_efuse_pkg::fuse_command_resp_t`	Fuse command response from the shim state machine.
`ext_boot_seq_done_i`	input	`logic`	External boot sequence done, active-high; the eFuse wrapper holds its released reset until it is set.
`ext_boot_seq_done_qual_o`	output	`logic`	ext_boot_seq_done_i synchronized to clk_smc_i and held set until cold reset.
`sep_security_disable_i`	input	`logic`	Security disable from the SEP eFuse controller, active-high; skips automatic fuse sensing and releases the shadow registers without it.
`fuse_reset_n_o`	output	`logic`	Efuse Released Reset. Fuse sensing done && external boot sequence done (includes memory repair and shadow reg override being complete) - the rest of SMC can now boot. Held low while the boot stall is set.
`fuse_reset_n_delayed_o`	output	`logic`	fuse_reset_n_o after 16 SMC clock pipe stages reset by the primary reset.
`fuse_sense_done_o`	output	`logic`	Fuse sensing done. High once shadow-register loading from the fuses completes.
`shadow_regs_o`	output	`smc_efuse_pkg::efuse_map_t`	eFuse shadow-register contents; zero until fuse sensing completes unless sep_security_disable_i is set.
`ndmreset_request_i`	input	`logic [smc_config_pkg::CpuClusterCount-1:0]`	Asynchronous NDM reset request from each external CPU cluster; synchronized to the SMC clock and raised as a peripheral interrupt.
`ndmreset_process_o`	output	`logic [smc_config_pkg::CpuClusterCount-1:0]`	Firmware response to each cluster's NDM reset request, from the NDMRESET_PROCESS register.
`powergood_i`	input	`logic`	Powergood, active-high; while low the reset unit holds the cold, primary and warm resets.
`rst_cold_ni`	input	`logic`	Cold reset, active-low, deglitched and extended in the reset unit.
`rst_cool_ni`	input	`logic`	Cool reset from the pin, active-low, deglitched in the reset unit into the primary reset.
`rst_cold_stable_ref_clk_no`	output	`logic`	De-glitched and extended cold reset, active-low, synchronized to the reference clock.
`powergood_stable_o`	output	`logic`	Powergood from the reset unit: falls with powergood_i and rises 32 reference clock cycles after it.
`rst_ext_wdt_ni`	input	`logic`	SEP watchdog reset, active-low; drives the watchdog reset in the reset unit and, once synchronized, a peripheral interrupt.
`smc_wdt_first_timeout_i`	input	`logic`	First-stage SMC watchdog timeout, passed to the reset unit.
`smc_wdt_second_timeout_i`	input	`logic`	Second-stage SMC watchdog timeout; asserts the watchdog reset in the reset unit.
`cfg_flr_pf_active_i`	input	`logic`	PCIe function-level reset request, active-high; starts the reset unit's isolation and cool reset sequence.
`isolate_req_o`	output	`logic [31:0]`	Per-subsystem isolation requests from the reset unit, raised by its registers, the isolate pin or the function-level reset sequence.
`skip_mem_repair_o`	output	`logic`	Asserted during a function-level reset to skip memory repair and MBIST.
`ss_reset_complete_i`	input	`logic [31:0]`	Per-subsystem reset complete acknowledgments, synchronized to the SMC clock in the reset unit.
`ss_config_o`	output	`logic [31:0]`	Per-subsystem configuration bits written through the reset-unit SS_CONFIG register; cleared by primary reset.
`ss_reset_ctrl_o`	output	`smc_reset_unit_pkg::reset_ctrl_t`	Per-subsystem cold and warm resets, hold controls and force-to-reference-clock select; the resets are not synchronized to the subsystem clock.
`rst_primary_ref_clk_no`	output	`logic`	Primary reset (cold, cool and function-level reset combined), active-low, synchronized to the reference clock.
`rst_primary_smc_clk_no`	output	`logic`	Primary reset, active-low, synchronized to the SMC clock; resets the peripheral crossbar and SMC-clock peripherals.
`rst_warm_smc_clk_no`	output	`logic`	Warm reset (primary, watchdog and fuse reset combined), active-low, synchronized to the SMC clock.
`rst_wdt_smc_clk_no`	output	`logic`	Watchdog reset from the SEP watchdog or the second-stage SMC watchdog timeout, active-low, synchronized to the SMC clock.
`rst_primary_periph_clk_no`	output	`logic`	Primary reset, active-low, synchronized to the peripheral clock.
`sync_irq_o`	output	`logic`	Global sync bit set by software through the reset-unit SYNC_REG register.
`jtag_reset_ctrl_i`	input	`smc_pkg::jtag_smc_reset_ctrl_t`	JTAG override selects and values for the fuse, cold, cool, warm and per-subsystem resets, in the TCK domain.
`sep_mailbox_interrupts_i`	input	`logic [7:0]`	SEP mailbox interrupts, placed on peripheral interrupt bits 7:0.
`axi_hang_irq_i`	input	`logic`	OR of the smc_base AXI hang detectors, placed on peripheral interrupt bit 30.
`peripheral_interrupts_o`	output	`logic [31:0]`	Peripheral interrupt vector to the SMC interrupt controller: SEP mailbox, telemetry, NDM reset, I3C, UART, AVSBus, I2C, SEP watchdog, eFuse locked-field, GPIO and AXI hang sources.
`gpio_interrupt_o`	output	`logic [smc_pkg::NumGpioWraps-1:0]`	Per-GPIO interrupt from the padring, on the SMC clock.
`uart_interrupt_o`	output	`logic [smc_config_pkg::NumUart-1:0]`	Per-UART interrupt on the peripheral clock, without the error and log-engine sources.
`i3c_dat_mem_src_i`	input	`i3c_pkg::dat_mem_src_t [smc_config_pkg::NumI3c-1:0]`	Read data from each I3C device address table memory.
`i3c_dat_mem_sink_o`	output	`i3c_pkg::dat_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	Request to each I3C device address table memory.
`i3c_dct_mem_src_i`	input	`i3c_pkg::dct_mem_src_t [smc_config_pkg::NumI3c-1:0]`	Read data from each I3C device characteristics table memory.
`i3c_dct_mem_sink_o`	output	`i3c_pkg::dct_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	Request to each I3C device characteristics table memory.
`i3c_rlt_mem_src_i`	input	`i3c_pkg::rlt_mem_src_t [smc_config_pkg::NumI3c-1:0]`	Read data from each I3C reverse-lookup table memory.
`i3c_rlt_mem_sink_o`	output	`i3c_pkg::rlt_mem_sink_t [smc_config_pkg::NumI3c-1:0]`	Request to each I3C reverse-lookup table memory.
`gated_clk_periph_i3c_o`	output	`logic`	Gated I3C peripheral clock (same domain as i3ccore_wrapper).
`avsbus_cur_state_debug_o`	output	`logic [16:0]`	AVSBus controller state, synchronized to the SMC clock.
`telemetry_debug_o`	output	`logic [smc_config_pkg::NumTelemetryReceivers-1:0][3:0]`	telemetry receiver debug (4 bits per; see telemetry_receiver.sv for field definitions).
`i2c_debug_o`	output	`logic [smc_config_pkg::NumI2c-1:0][3:0]`	I2C debug (4 bits per I2C; see i2c_core.sv for field definitions).
`efuse_debug_o`	output	`logic [9:0]`	eFuse controller status for the SMC debug bus: shadow-register write and read locks, program and read locks, write-setup-only, LC-state access, read and program timeouts, request error and secure-test-mode block, from bit 0 upward.